KMAC/UNMASKED Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	9.330s	388.889us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.880s	18.827us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.740s	186.978us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.750s	2.999ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.980s	1.524ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.070s	82.286us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.740s	186.978us	1	1	100.00
		kmac_csr_aliasing	6.980s	1.524ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.680s	29.142us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.310s	36.194us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	21.828m	140.918ms	1	1	100.00
V2	burst_write	kmac_burst_write	25.630s	3.507ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.020s	651.846us	1	1	100.00
		kmac_test_vectors_sha3_256	28.660s	1.697ms	1	1	100.00
		kmac_test_vectors_sha3_384	27.030s	1.211ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.930s	4.524ms	1	1	100.00
		kmac_test_vectors_shake_128	2.331m	79.656ms	1	1	100.00
		kmac_test_vectors_shake_256	1.460m	4.932ms	1	1	100.00
		kmac_test_vectors_kmac	2.580s	1.113ms	1	1	100.00
		kmac_test_vectors_kmac_xof	2.890s	103.773us	1	1	100.00
V2	sideload	kmac_sideload	2.836m	36.551ms	1	1	100.00
V2	app	kmac_app	3.179m	13.108ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.159m	22.646ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	28.510s	2.072ms	1	1	100.00
V2	error	kmac_error	3.902m	17.913ms	1	1	100.00
V2	key_error	kmac_key_error	8.560s	1.664ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.259m	10.057ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.350s	3.535ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	20.360s	14.152ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	8.440s	913.211us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	12.080s	728.131us	1	1	100.00
V2	stress_all	kmac_stress_all	28.924m	363.379ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.710s	15.552us	1	1	100.00
V2	alert_test	kmac_alert_test	1.730s	58.761us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.940s	294.387us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.940s	294.387us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.880s	18.827us	1	1	100.00
		kmac_csr_rw	1.740s	186.978us	1	1	100.00
		kmac_csr_aliasing	6.980s	1.524ms	1	1	100.00
		kmac_same_csr_outstanding	2.870s	76.381us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.880s	18.827us	1	1	100.00
		kmac_csr_rw	1.740s	186.978us	1	1	100.00
		kmac_csr_aliasing	6.980s	1.524ms	1	1	100.00
		kmac_same_csr_outstanding	2.870s	76.381us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.140s	24.349us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.140s	24.349us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.140s	24.349us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.140s	24.349us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.270s	46.588us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	20.580s	8.781ms	1	1	100.00
		kmac_tl_intg_err	3.020s	162.679us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.020s	162.679us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	12.080s	728.131us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	9.330s	388.889us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.836m	36.551ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.140s	24.349us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	20.580s	8.781ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	20.580s	8.781ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	20.580s	8.781ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	9.330s	388.889us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	12.080s	728.131us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	20.580s	8.781ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	46.830s	8.364ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	9.330s	388.889us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.230m	6.071ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.1288196274936314915160041678246402630362863814085387165253117906411507003847
      Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10057423700 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7085e000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
        UVM_INFO @ 10057423700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.74909892566817218054670113781414832393765525984322720874976618657729108360072
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  46587844 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  46587844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---