209351c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.033m | 10.799ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 24.186us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 19.566us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 3.000s | 22.528us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 3.000s | 13.023us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 4.403us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 19.566us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 3.000s | 13.023us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 56.000s | 18.861ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 45.000s | 1.020ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 39.000s | 2.124ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 3.000s | 29.487us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 3.887us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 3.887us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 24.186us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 19.566us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 13.023us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 45.892us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 24.186us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 19.566us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 13.023us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 45.892us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 3.000s | 26.569us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 11.851us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.38855484498035412299756202085052824095991660089711959032768040692878727936812
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 3887253 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xbcd5b7d0 a_data = 0x7bac6cee a_mask = 0x3 a_size = 0x1 a_param = 0x0 a_source = 0xe6 a_opcode = Invalid, value: 3 a_user = 0x24652 d_data = 0xf40f44a d_size = 0x0 d_param = 0x0 d_source = 0x97 d_opcode = AccessAck d_error = 0 d_user = 1110000000 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 3887253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.2548590350711941752888665464891909113379176978742004589637190059456912905731
Line 99, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 11851148 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x1dada914 a_data = 0x53490e92 a_mask = 0x2 a_size = 0x1 a_param = 0x0 a_source = 0x6a a_opcode = PutPartialData a_user = 0x254c9 d_data = 0xbd18511b d_size = 0x0 d_param = 0x0 d_source = 0xf2 d_opcode = AccessAck d_error = 0 d_user = 10001000110110 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 11851148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.33220732358722028397975474788043676526546990559916771822998140678147299241952
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 4402971 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xcb0af73f a_data = 0x42463118 a_mask = 0x3 a_size = 0x1 a_param = 0x0 a_source = 0xf0 a_opcode = PutPartialData a_user = 0x248fa d_data = 0xe5752abc d_size = 0x2 d_param = 0x0 d_source = 0x1f d_opcode = AccessAckData d_error = 0 d_user = 1111001000110 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4402971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---