OTBN Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	266.017us	1	1	100.00
V1	single_binary	otbn_single	8.000s	18.245us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	28.649us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	32.298us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	38.200us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	152.488us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	67.132us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	32.298us	1	1	100.00
		otbn_csr_aliasing	5.000s	152.488us	1	1	100.00
V1	mem_walk	otbn_mem_walk	18.000s	656.798us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	12.000s	385.027us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	28.000s	110.551us	0	1	0.00
V2	multi_error	otbn_multi_err	47.000s	156.658us	1	1	100.00
V2	back_to_back	otbn_multi	33.000s	297.022us	1	1	100.00
V2	stress_all	otbn_stress_all	1.150m	1.162ms	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	87.563us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	30.637us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	57.240us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	51.558us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	40.932us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	93.411us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	93.411us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	28.649us	1	1	100.00
		otbn_csr_rw	6.000s	32.298us	1	1	100.00
		otbn_csr_aliasing	5.000s	152.488us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	22.670us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	28.649us	1	1	100.00
		otbn_csr_rw	6.000s	32.298us	1	1	100.00
		otbn_csr_aliasing	5.000s	152.488us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	22.670us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	9.000s	77.503us	1	1	100.00
		otbn_dmem_err	9.000s	64.658us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	197.422us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	18.631us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	55.123us	1	1	100.00
		otbn_urnd_err	8.000s	10.913us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	17.827us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	12.483us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	41.364us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
		otbn_tl_intg_err	14.000s	61.967us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	18.000s	327.415us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	266.017us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	64.658us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	77.503us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	14.000s	61.967us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	87.563us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	77.503us	1	1	100.00
		otbn_dmem_err	9.000s	64.658us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	30.637us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	17.827us	1	1	100.00
		otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	77.503us	1	1	100.00
		otbn_dmem_err	9.000s	64.658us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	30.637us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	17.827us	1	1	100.00
		otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	87.563us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	77.503us	1	1	100.00
		otbn_dmem_err	9.000s	64.658us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	30.637us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	17.827us	1	1	100.00
		otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	85.961us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	32.520us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	59.000s	1.022ms	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	59.000s	1.022ms	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	17.939us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	65.809us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	182.359us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	182.359us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	16.127us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	33.000s	297.022us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	18.842us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	18.245us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	17.000s	1.336ms	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.683m	3.125ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:424) [otbn_reset_vseq] Check failed exp_end_addr == cfg.model_agent_cfg.vif.stop_pc (* [*] vs * [*]) has 1 failures:

  • Test otbn_reset has 1 failures.

    • 0.otbn_reset.58190302616815612848581479698485163031956862665625285251829525412429771518410
      Line 154, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest/run.log

        UVM_FATAL @ 110551259 ps: (otbn_base_vseq.sv:424) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed exp_end_addr == cfg.model_agent_cfg.vif.stop_pc (5040 [0x13b0] vs 5044 [0x13b4])
        UVM_INFO @ 110551259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.77968876343969694174773009800245409895338813364987800560787263039415765761524
      Line 501, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3125003089 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 3125003089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.111246157147032593564229455607072877778409749032348178429782490992774786549098
      Line 123, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 1336274540 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1336274540 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @ 1336274540 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @ 1336274540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---