ROM_CTRL/32KB Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.800s	183.131us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.070s	541.433us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.630s	726.589us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.530s	129.538us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.030s	169.570us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.710s	2.017ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.630s	726.589us	1	1	100.00
		rom_ctrl_csr_aliasing	5.030s	169.570us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.970s	9.860ms	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.120s	555.877us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.240s	184.952us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	10.730s	1.160ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.660s	1.080ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.790s	372.499us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.510s	1.583ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.510s	1.583ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.070s	541.433us	1	1	100.00
		rom_ctrl_csr_rw	4.630s	726.589us	1	1	100.00
		rom_ctrl_csr_aliasing	5.030s	169.570us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.640s	289.285us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.070s	541.433us	1	1	100.00
		rom_ctrl_csr_rw	4.630s	726.589us	1	1	100.00
		rom_ctrl_csr_aliasing	5.030s	169.570us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.640s	289.285us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	21.220s	819.164us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.473m	1.131ms	1	1	100.00
		rom_ctrl_tl_intg_err	24.210s	392.342us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.473m	1.131ms	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.473m	1.131ms	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.473m	1.131ms	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.473m	1.131ms	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.800s	183.131us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.800s	183.131us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.800s	183.131us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.210s	392.342us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
		rom_ctrl_kmac_err_chk	7.660s	1.080ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.250s	414.011us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	21.220s	819.164us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.473m	1.131ms	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	52.420s	1.182ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.81881741282190608243583025082415178546184239359251104892520838756966534128000
      Line 84, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 414011023 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 414011023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---