ROM_CTRL/64KB Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.410s 771.541us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.140s 622.673us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.670s 922.870us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.830s 602.159us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.270s 292.215us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.330s 768.343us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.670s 922.870us 1 1 100.00
rom_ctrl_csr_aliasing 7.270s 292.215us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.630s 576.273us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.840s 215.184us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.950s 216.884us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.170s 1.121ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.110s 1.059ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.950s 554.292us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.350s 511.557us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.350s 511.557us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.140s 622.673us 1 1 100.00
rom_ctrl_csr_rw 6.670s 922.870us 1 1 100.00
rom_ctrl_csr_aliasing 7.270s 292.215us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.970s 1.096ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.140s 622.673us 1 1 100.00
rom_ctrl_csr_rw 6.670s 922.870us 1 1 100.00
rom_ctrl_csr_aliasing 7.270s 292.215us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.970s 1.096ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 31.030s 2.149ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.053m 2.741ms 1 1 100.00
rom_ctrl_tl_intg_err 1.052m 907.717us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.053m 2.741ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.053m 2.741ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.053m 2.741ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.053m 2.741ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.410s 771.541us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.410s 771.541us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.410s 771.541us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.052m 907.717us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.110s 1.059ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.494m 40.456ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 31.030s 2.149ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.053m 2.741ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.030m 10.921ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00