| V1 |
random |
rv_timer_random |
1.580s |
28.699us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.480s |
36.947us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.590s |
42.088us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.740s |
67.238us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.640s |
30.369us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.720s |
55.976us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.590s |
42.088us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.640s |
30.369us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.660s |
57.630us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.650s |
823.275us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
4.565m |
446.737ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
4.565m |
446.737ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
2.720s |
1.224ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.510s |
15.292us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.490s |
36.829us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.110s |
116.559us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.110s |
116.559us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.480s |
36.947us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.590s |
42.088us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.640s |
30.369us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.450s |
43.216us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.480s |
36.947us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.590s |
42.088us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.640s |
30.369us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.450s |
43.216us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
2.090s |
238.569us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.900s |
79.114us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.900s |
79.114us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.480s |
16.246us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.500s |
40.389us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
12.440s |
6.234ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |