SPI_DEVICE/1R1W Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.287m	121.150ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.750s	36.350us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.040s	38.794us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.860s	356.819us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.800s	1.082ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.420s	70.530us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.040s	38.794us	1	1	100.00
		spi_device_csr_aliasing	14.800s	1.082ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.500s	22.397us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.110s	35.939us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.760s	22.130us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.640s	5.764us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.670s	5.883us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.430s	250.436us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.430s	250.436us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.350s	3.087ms	1	1	100.00
		spi_device_tpm_sts_read	1.530s	23.238us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.240s	1.198ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	10.830s	9.044ms	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.180s	1.421ms	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.180s	1.421ms	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.750s	342.674us	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.750s	342.674us	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.750s	342.674us	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.750s	342.674us	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.750s	342.674us	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	9.090s	7.093ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.980s	399.189us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.980s	399.189us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.980s	399.189us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.600s	2.132ms	1	1	100.00
		spi_device_read_buffer_direct	13.800s	4.155ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.980s	399.189us	1	1	100.00
		spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	quad_spi	spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	dual_spi	spi_device_flash_all	4.530s	774.813us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.940s	272.463us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.940s	272.463us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.287m	121.150ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.032m	20.163ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.957m	34.080ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.520s	19.731us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.690s	25.551us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.190s	805.240us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.190s	805.240us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.750s	36.350us	1	1	100.00
		spi_device_csr_rw	2.040s	38.794us	1	1	100.00
		spi_device_csr_aliasing	14.800s	1.082ms	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	362.114us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.750s	36.350us	1	1	100.00
		spi_device_csr_rw	2.040s	38.794us	1	1	100.00
		spi_device_csr_aliasing	14.800s	1.082ms	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	362.114us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.820s	69.823us	1	1	100.00
		spi_device_tl_intg_err	5.690s	573.347us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.690s	573.347us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	49.780s	7.729ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.110522906571212776300369566516684821383617258415611115714414776303806369114834
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3084245 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[60])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3084245 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3084245 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[956])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.2848803246461385613488200714062250066075015111397427898670196763218445144481
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3153717 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2fecf [110000101111111011001111] vs 0x0 [0])
        UVM_ERROR @   3240717 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x634073 [11000110100000001110011] vs 0x0 [0])
        UVM_ERROR @   3325717 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd8eff0 [110110001110111111110000] vs 0x0 [0])
        UVM_ERROR @   3424717 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x58e8f8 [10110001110100011111000] vs 0x0 [0])
        UVM_ERROR @   3508717 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd90baf [110110010000101110101111] vs 0x0 [0])