UART Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.150s	988.667us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.700s	26.740us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.650s	15.087us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.270s	584.136us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.600s	16.866us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.540s	19.767us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.650s	15.087us	1	1	100.00
		uart_csr_aliasing	1.600s	16.866us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.083m	60.273ms	1	1	100.00
V2	parity	uart_smoke	2.150s	988.667us	1	1	100.00
		uart_tx_rx	1.083m	60.273ms	1	1	100.00
V2	parity_error	uart_intr	9.000s	8.418ms	1	1	100.00
		uart_rx_parity_err	22.500s	28.771ms	1	1	100.00
V2	watermark	uart_tx_rx	1.083m	60.273ms	1	1	100.00
		uart_intr	9.000s	8.418ms	1	1	100.00
V2	fifo_full	uart_fifo_full	18.280s	18.895ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	2.340m	114.697ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	19.850s	68.368ms	1	1	100.00
V2	rx_frame_err	uart_intr	9.000s	8.418ms	1	1	100.00
V2	rx_break_err	uart_intr	9.000s	8.418ms	1	1	100.00
V2	rx_timeout	uart_intr	9.000s	8.418ms	1	1	100.00
V2	perf	uart_perf	14.626m	25.904ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.860s	5.857ms	1	1	100.00
V2	line_loopback	uart_loopback	4.860s	5.857ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	7.020s	4.182ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.290s	39.601ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.970s	1.147ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	21.620s	4.095ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.516m	126.325ms	1	1	100.00
V2	stress_all	uart_stress_all	1.262m	55.223ms	1	1	100.00
V2	alert_test	uart_alert_test	1.620s	20.409us	1	1	100.00
V2	intr_test	uart_intr_test	1.720s	44.712us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.400s	37.068us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.400s	37.068us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.700s	26.740us	1	1	100.00
		uart_csr_rw	1.650s	15.087us	1	1	100.00
		uart_csr_aliasing	1.600s	16.866us	1	1	100.00
		uart_same_csr_outstanding	1.610s	19.930us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.700s	26.740us	1	1	100.00
		uart_csr_rw	1.650s	15.087us	1	1	100.00
		uart_csr_aliasing	1.600s	16.866us	1	1	100.00
		uart_same_csr_outstanding	1.610s	19.930us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	2.010s	580.487us	1	1	100.00
		uart_tl_intg_err	1.890s	100.454us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.890s	100.454us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	29.420s	3.305ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.46126876609648874258408132999080790736908859402517958853454929767405008805167
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 3771812931 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 3771812931 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3780098579 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 3780098579 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3780210823 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0