CHIP Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: `209351c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.097m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.097m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.130m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	22.955s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	21.333s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.675m	7.189ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.675m	7.189ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.675m	7.189ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	28.330s	10.300us	0	1	0.00
		chip_sw_example_manufacturer	2.464m		0	1	0.00
		chip_sw_example_concurrency	3.415m	3.411ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.443s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.440s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.330s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.330s		0	1	0.00
V1	xbar_smoke	xbar_smoke	10.300s	12.966us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.483m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.075m	9.955ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.087m	5.505ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	15.762s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	20.276s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.447s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	18.174s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.170s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.170s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.015m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.906m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.215m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.215m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.373m	3.219ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.658m	5.602ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.666m	14.576ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.437s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.899s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.523m	12.250ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.691m	4.231ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.022m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.022m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	15.980s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.732m	3.821ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.732m	3.821ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.962m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.756m	3.731ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.586m	4.968ms	1	1	100.00
		chip_sw_aes_idle	3.619m	5.673ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.308m	5.185ms	1	1	100.00
		chip_sw_kmac_idle	3.454m	4.720ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.760m	12.016ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.926m	12.017ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.537m	12.016ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.414m	12.019ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.889s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.909s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.054s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.094s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.650s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.205s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.163s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.889s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.909s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.054s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.094s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.650s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.205s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.163s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.511s		0	1	0.00
		chip_sw_aes_enc_jitter_en	34.400s	10.120us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.380s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.240s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.990s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.283s		0	1	0.00
		chip_sw_clkmgr_jitter	3.373m	5.894ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.258m	3.931ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	14.048s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.110s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	35.500s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	40.960s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	41.280s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.120s	10.240us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.240s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.759s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.773s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.004s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.796m	14.563ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.481m	14.909ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.732m	3.821ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.501s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.481m	14.909ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	16.796s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	18.905s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.098s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	18.655s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	14.774s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.796m	14.563ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.666m	14.576ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.855m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.709m	8.352ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.287m	8.006ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.442m	5.261ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.796m	14.563ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.404s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.481s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.796m	14.563ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.551s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.287m	8.006ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.514s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.970s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.537s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.458s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.408s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.315s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.481s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.642s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.297m	5.775ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	37.665s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.176s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.945s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	17.511s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.518m	8.392ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.386m	12.407ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	14.799s		0	1	0.00
		chip_prim_tl_access	4.264m	9.654ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.889s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.909s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.054s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.094s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.650s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.205s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.163s		0	1	0.00
		chip_rv_dm_lc_disabled	9.523m	12.250ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.345m	4.680ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	34.400s	10.120us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.483m	3.484ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.619m	5.673ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.599m	4.870ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	35.380s	10.280us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.308m	5.185ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.576m	5.439ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.066m	4.760ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	36.990s	10.380us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.518m	8.392ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	40.480s	10.220us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.275m	5.666ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.454m	4.720ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.326s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.326s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.222s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.821m	4.672ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.921s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.518m	8.392ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.240s	10.120us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.852s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.511s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.586m	4.968ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.586m	4.968ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.586m	4.968ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.684m	6.193ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.386m	12.407ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.386m	12.407ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.667m	6.256ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.283s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.799s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.796m	14.563ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.215m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.684m	6.193ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.518m	8.392ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.667m	6.256ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.287m	4.970ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.684m	6.193ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.518m	8.392ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.667m	6.256ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.287m	4.970ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.239s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.642s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	37.665s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.176s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.945s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	17.511s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.986s		0	1	0.00
		chip_prim_tl_access	4.264m	9.654ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.264m	9.654ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	42.424s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	40.112s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.759s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.511s		0	1	0.00
		chip_sw_aes_enc_jitter_en	34.400s	10.120us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.380s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.240s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.990s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.283s		0	1	0.00
		chip_sw_clkmgr_jitter	3.373m	5.894ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.677m	10.157ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.677m	10.157ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.028m	4.193ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.422m	4.314ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.339m	3.851ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.148m	4.827ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.010m	5.304ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.965m	5.147ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.287m	4.970ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.855m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.855m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.593m	3.421ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.321m	4.648ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.775m	4.703ms	1	1	100.00
		chip_sw_csrng_smoketest	3.244m	5.020ms	1	1	100.00
		chip_sw_gpio_smoketest	3.899m	4.026ms	1	1	100.00
		chip_sw_hmac_smoketest	4.321m	4.672ms	1	1	100.00
		chip_sw_kmac_smoketest	3.617m	4.152ms	1	1	100.00
		chip_sw_otbn_smoketest	5.221m	6.170ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.972m	5.941ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.208m	3.718ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.332m	5.671ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.262m	4.263ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.548m	4.082ms	1	1	100.00
		chip_sw_uart_smoketest	3.579m	4.133ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.673s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.443s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.483m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.076s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.098m	5.207ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.854m	5.096ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.051m	6.260ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.246m	4.172ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.813s		0	1	0.00
		chip_rv_dm_lc_disabled	9.523m	12.250ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.282s		0	1	0.00
		chip_sw_lc_walkthrough_prod	21.541s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.213s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.562s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.813s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.762s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.833s		0	1	0.00
		rom_volatile_raw_unlock	10.983s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.811s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.453m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.335m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.673m	3.477ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.673m	3.477ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.330s		0	1	0.00
		chip_same_csr_outstanding	8.710s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.330s		0	1	0.00
		chip_same_csr_outstanding	8.710s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.675m	255.022us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.700s	11.616us	1	1	100.00
		xbar_smoke_large_delays	4.581m	2.375ms	1	1	100.00
		xbar_smoke_slow_rsp	5.698m	2.121ms	1	1	100.00
		xbar_random_zero_delays	1.382m	71.602us	1	1	100.00
		xbar_random_large_delays	10.085m	4.832ms	1	1	100.00
		xbar_random_slow_rsp	7.314m	2.657ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	53.900s	102.191us	1	1	100.00
		xbar_error_and_unmapped_addr	9.710s	9.410us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.255m	377.550us	1	1	100.00
		xbar_error_and_unmapped_addr	9.710s	9.410us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	6.052m	932.210us	1	1	100.00
		xbar_access_same_device_slow_rsp	27.927m	10.560ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.356m	245.457us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	11.226m	1.761ms	1	1	100.00
		xbar_stress_all_with_error	2.905m	171.245us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	39.371m	2.012ms	1	1	100.00
		xbar_stress_all_with_reset_error	25.052m	1.034ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.038s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.653s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.893s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.093s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.298s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.851s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.605s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.280s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.382s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.897s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.988s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.968s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.712s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.389s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.182s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.833s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.971s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.165s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.505s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.940s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.974s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.376s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.865s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.256s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.673s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.724s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.478s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.501s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.600s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.726s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.080s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.343s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.123s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.213s		0	1	0.00
		rom_e2e_asm_init_dev	12.321s		0	1	0.00
		rom_e2e_asm_init_prod	11.335s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.772s		0	1	0.00
		rom_e2e_asm_init_rma	11.390s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.902s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.426s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.339s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.852s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.815m	5.537ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.492m	4.737ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.981s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.204s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.848s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.503s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.796m	14.563ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	28.365s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.074m	15.197ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.275s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.649s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.981s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.204s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.848s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.902s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.600s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.979s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.028m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.079m	12.352ms	1	1	100.00
		chip_plic_all_irqs_0	8.810m	6.952ms	1	1	100.00
		chip_plic_all_irqs_10	10.452m	7.821ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.510m	3.990ms	1	1	100.00
		chip_sw_dma_abort	4.462m	4.320ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.933s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.484s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.335s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.825s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.565s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.749s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.621s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.082s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.229s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.591s		0	1	0.00
		chip_sw_mbx_smoketest	4.234m	3.873ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.50246987441418068994375184001493937834060541368498730596538052952586704733924
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (eacf37)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 130.393s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.79645535484654766311379034907706809401114685347125092307174801215097654635187
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (30b4fe)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 122.520s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.62871535284321628749780871312137493185479317567548912924091195918771228177591
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (da48f9)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 110.238s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.29774998164585852190185346253300535907299387075691678438681531358126526468329
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (0dbfb4)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 103.687s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.42978524435626725277011152608503512229929378588424753814860804918117470639317
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (729e4c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 115.744s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.101038596400870874570202312985106080141536407067078976247259580656962109676396
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.99366214383914550193321690230242926458018370366254781546209876503916104486248
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.114577947243613760709813986496882456835294733239223473554356091947776664492060
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.79009729378202084390408148898344394407803040972199553300457293297068782347626
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.27462753603509666279352624467754380816501298172263082808453389494054932484869
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.9634165333291388254591522672114575400013874423226546728218387786929659535947
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12016.365106 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.365106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.88584882972769579800851192863655094810294307071376793575047334990099776212578
Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12016.546863 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.546863 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.26887716333935743146984128409980055833011699419396298398099751855419334127774
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12016.086840 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.086840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.25165695923404107350779725525806536173540737324345775194328833362429743508248
Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.983984 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.983984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.28729890253202505381260781272491307950821617520020201106222070727200151416469
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.58123355794786045897182424297556814230706345479411982980320110357346780725355
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.66668587508236415792069906206546978446225117209620160835953606965018412849222
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.29160221265249699852818112803469468198907551235217697496685429956230850980855
Line 492, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.520265 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.520265 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.33688402006832811694834597812160081205849306736182981787087406469579538398476
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18015.936855 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.936855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.47743738821451998429386710034990518390821691007274474561009726130099866216963
Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.092153 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.092153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.77096719851591956996203785956564200303291015833628712047433076644305789579717
Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8391.890474 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (48632059646087941459623476551698961356847171788188284940679859313821612341252 [0x6b84c533994264c911d3b900e7ab471d9254340a82406ba63498eb7099857804] vs 104327256839088110194569510939795104238053347814062232044022906778768731065826 [0xe6a7228384d7eb412d0a44f4b745fe8348451e2b1cfe4ce6ba1f9cbe9e2ccde2])
  UVM_INFO @ 8391.890474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.91045995709953588022774607272990931006524000598014105767885777915718632024684
Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5774.933622 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (96464431411668146551222157428942282144300831712543325545240227167285436707843 [0xd544eeef25b1c5b7fd16a4d9f7104423a3b5dc9121d74c7da854a4b2a66b7403] vs 22576338809985627135767704232104477356972829577243621310197825009351820542045 [0x31e9c143bd71d679dc75b1abdddb118f4d6bb98cc42db2df4e9bfcd9d257805d])
  UVM_INFO @ 5774.933622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.55419457965442755239550922698172092487187844171534915217064611553071171136368
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3218.878049 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hac3ec42b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h0  a_user: 'h2691a  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3218.878049 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.1027605743003250872991290757126602671359683677778823510687335879446901851792
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5602.197925 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h2d387d75  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h1  a_user: 'h248d4  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5602.197925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.39722195874334280617532205652252682602330160337722248467265741525578449948197
    Line 404, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.48261818424384873299622813696246609928973562833546792442080241352043127584812
    Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5505.003466 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5505.003466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.56829309596401874386873311180128972381641816637908891372875402368842719090839
    Line 681, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8005.504158 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8005.504158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.85425249652750719867997653506803409963247651914660564089923297839759144707545
    Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4192.807072 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4192.807072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.34121964261821139044189662427671149563549524753685947531782373039818092250741
    Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4314.286812 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4314.286812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.73817313813203337600647393154634110950212044720446946663461127338226555917707
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3821.084128 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3821.084128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.109159515210252549486993512722229161014389757791352328412285851610486088630675
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4827.046122 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4827.046122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.115307630529077601299340563875253590704646087740189990822997703244796885311053
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.30344635951199136031464036945987367040555942263784151380631862353748113314210
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3476.553898 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3476.553898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.113176491713646118715804853332961249032359699747904947551354904475823770693650
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14575.998632 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14575.998632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.103730922186207039038913800641777624203583188435371796646147239169564557686965
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.52828558788155431852360666173132291969856296826856501309434935623685830477924
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4319.839260 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4319.839260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```