AES/MASKED Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	85.348us	1	1	100.00
V1	smoke	aes_smoke	7.000s	379.653us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	87.995us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	70.036us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	701.824us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	70.921us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	298.912us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	70.036us	1	1	100.00
		aes_csr_aliasing	5.000s	70.921us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	7.000s	379.653us	1	1	100.00
		aes_config_error	4.000s	199.487us	1	1	100.00
		aes_stress	5.000s	126.636us	1	1	100.00
V2	key_length	aes_smoke	7.000s	379.653us	1	1	100.00
		aes_config_error	4.000s	199.487us	1	1	100.00
		aes_stress	5.000s	126.636us	1	1	100.00
V2	back2back	aes_stress	5.000s	126.636us	1	1	100.00
		aes_b2b	6.000s	87.585us	1	1	100.00
V2	backpressure	aes_stress	5.000s	126.636us	1	1	100.00
V2	multi_message	aes_smoke	7.000s	379.653us	1	1	100.00
		aes_config_error	4.000s	199.487us	1	1	100.00
		aes_stress	5.000s	126.636us	1	1	100.00
		aes_alert_reset	5.000s	150.967us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	62.971us	1	1	100.00
		aes_config_error	4.000s	199.487us	1	1	100.00
		aes_alert_reset	5.000s	150.967us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	336.844us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	1.269ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	150.967us	1	1	100.00
V2	stress	aes_stress	5.000s	126.636us	1	1	100.00
V2	sideload	aes_stress	5.000s	126.636us	1	1	100.00
		aes_sideload	6.000s	306.004us	1	1	100.00
V2	deinitialization	aes_deinit	6.000s	89.541us	1	1	100.00
V2	stress_all	aes_stress_all	9.000s	300.240us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	70.293us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	410.757us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	410.757us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	87.995us	1	1	100.00
		aes_csr_rw	4.000s	70.036us	1	1	100.00
		aes_csr_aliasing	5.000s	70.921us	1	1	100.00
		aes_same_csr_outstanding	5.000s	93.425us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	87.995us	1	1	100.00
		aes_csr_rw	4.000s	70.036us	1	1	100.00
		aes_csr_aliasing	5.000s	70.921us	1	1	100.00
		aes_same_csr_outstanding	5.000s	93.425us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	8.000s	138.831us	1	1	100.00
V2S	fault_inject	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_cipher_fi	5.000s	56.424us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	214.045us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	214.045us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	214.045us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	214.045us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	130.264us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	899.771us	1	1	100.00
		aes_tl_intg_err	5.000s	180.574us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	180.574us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	150.967us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	214.045us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	379.653us	1	1	100.00
		aes_stress	5.000s	126.636us	1	1	100.00
		aes_alert_reset	5.000s	150.967us	1	1	100.00
		aes_core_fi	5.000s	120.288us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	214.045us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	80.779us	1	1	100.00
		aes_stress	5.000s	126.636us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	126.636us	1	1	100.00
		aes_sideload	6.000s	306.004us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	80.779us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	80.779us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	80.779us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	80.779us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	80.779us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	126.636us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	126.636us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	1.930ms	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_cipher_fi	5.000s	56.424us	1	1	100.00
		aes_ctr_fi	4.000s	59.124us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	1.930ms	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_cipher_fi	5.000s	56.424us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	56.424us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	1.930ms	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_ctr_fi	4.000s	59.124us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_cipher_fi	5.000s	56.424us	1	1	100.00
		aes_ctr_fi	4.000s	59.124us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	150.967us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_cipher_fi	5.000s	56.424us	1	1	100.00
		aes_ctr_fi	4.000s	59.124us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_cipher_fi	5.000s	56.424us	1	1	100.00
		aes_ctr_fi	4.000s	59.124us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_ctr_fi	4.000s	59.124us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	1.930ms	1	1	100.00
		aes_control_fi	4.000s	58.452us	1	1	100.00
		aes_cipher_fi	5.000s	56.424us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.000s	39.587us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.37380323141452703944997464038782671466228116874161313761567413979137028201583
      Line 139, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  39587189 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  39587189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---