DMA Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	636.975us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	340.725us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	1.328ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	18.471us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	119.375us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	14.000s	1.483ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	1.311ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	112.510us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	119.375us	1	1	100.00
		dma_csr_aliasing	6.000s	1.311ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	30.000s	2.523ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.100m	97.329ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	32.833m	465.680ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.533m	21.075ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.100m	97.329ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	439.983us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.933m	83.770ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	98.004us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	91.852us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	91.852us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	18.471us	1	1	100.00
		dma_csr_rw	4.000s	119.375us	1	1	100.00
		dma_csr_aliasing	6.000s	1.311ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	27.176us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	18.471us	1	1	100.00
		dma_csr_rw	4.000s	119.375us	1	1	100.00
		dma_csr_aliasing	6.000s	1.311ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	27.176us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	131.523us	1	1	100.00
		dma_generic_stress	3.533m	21.075ms	1	1	100.00
		dma_handshake_stress	5.100m	97.329ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	220.466us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.133m	75.959ms	1	1	100.00
		dma_longer_transfer	15.000s	1.275ms	1	1	100.00
		TOTAL			21	21	100.00