EDN Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.830s	18.225us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.760s	32.310us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.800s	36.245us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.500s	270.039us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.900s	19.713us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.990s	106.003us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.800s	36.245us	1	1	100.00
		edn_csr_aliasing	1.900s	19.713us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.090s	65.426us	1	1	100.00
V2	csrng_commands	edn_genbits	2.090s	65.426us	1	1	100.00
V2	genbits	edn_genbits	2.090s	65.426us	1	1	100.00
V2	interrupts	edn_intr	1.590s	32.210us	1	1	100.00
V2	alerts	edn_alert	1.700s	41.854us	1	1	100.00
V2	errs	edn_err	1.930s	26.954us	1	1	100.00
V2	disable	edn_disable	1.610s	31.792us	1	1	100.00
		edn_disable_auto_req_mode	1.850s	30.994us	1	1	100.00
V2	stress_all	edn_stress_all	3.600s	725.465us	1	1	100.00
V2	intr_test	edn_intr_test	1.780s	30.073us	1	1	100.00
V2	alert_test	edn_alert_test	1.860s	57.880us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.620s	52.028us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.620s	52.028us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.760s	32.310us	1	1	100.00
		edn_csr_rw	1.800s	36.245us	1	1	100.00
		edn_csr_aliasing	1.900s	19.713us	1	1	100.00
		edn_same_csr_outstanding	1.650s	55.955us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.760s	32.310us	1	1	100.00
		edn_csr_rw	1.800s	36.245us	1	1	100.00
		edn_csr_aliasing	1.900s	19.713us	1	1	100.00
		edn_same_csr_outstanding	1.650s	55.955us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.380s	2.153ms	1	1	100.00
		edn_tl_intg_err	2.830s	299.793us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.660s	153.974us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.700s	41.854us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.380s	2.153ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.380s	2.153ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.380s	2.153ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.380s	2.153ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.700s	41.854us	1	1	100.00
		edn_sec_cm	7.380s	2.153ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.700s	41.854us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.830s	299.793us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	42.440s	5.399ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00