HMAC Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 1.590s 80.443us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.600s 44.575us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.870s 54.326us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.090s 553.286us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.610s 2.928ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.730s 209.004us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.870s 54.326us 1 1 100.00
hmac_csr_aliasing 6.610s 2.928ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 58.250s 7.235ms 1 1 100.00
V2 back_pressure hmac_back_pressure 58.850s 5.370ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.190s 1.637ms 1 1 100.00
hmac_test_sha384_vectors 19.570s 229.298us 1 1 100.00
hmac_test_sha512_vectors 23.890s 466.932us 1 1 100.00
hmac_test_hmac256_vectors 8.060s 2.164ms 1 1 100.00
hmac_test_hmac384_vectors 10.840s 1.029ms 1 1 100.00
hmac_test_hmac512_vectors 9.790s 285.849us 1 1 100.00
V2 burst_wr hmac_burst_wr 20.180s 4.506ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.958m 2.508ms 1 1 100.00
V2 error hmac_error 1.333m 36.499ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 54.310s 9.401ms 1 1 100.00
V2 save_and_restore hmac_smoke 1.590s 80.443us 1 1 100.00
hmac_long_msg 58.250s 7.235ms 1 1 100.00
hmac_back_pressure 58.850s 5.370ms 1 1 100.00
hmac_datapath_stress 4.958m 2.508ms 1 1 100.00
hmac_burst_wr 20.180s 4.506ms 1 1 100.00
hmac_stress_all 5.080s 115.049us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 1.590s 80.443us 1 1 100.00
hmac_long_msg 58.250s 7.235ms 1 1 100.00
hmac_back_pressure 58.850s 5.370ms 1 1 100.00
hmac_datapath_stress 4.958m 2.508ms 1 1 100.00
hmac_wipe_secret 54.310s 9.401ms 1 1 100.00
hmac_test_sha256_vectors 9.190s 1.637ms 1 1 100.00
hmac_test_sha384_vectors 19.570s 229.298us 1 1 100.00
hmac_test_sha512_vectors 23.890s 466.932us 1 1 100.00
hmac_test_hmac256_vectors 8.060s 2.164ms 1 1 100.00
hmac_test_hmac384_vectors 10.840s 1.029ms 1 1 100.00
hmac_test_hmac512_vectors 9.790s 285.849us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 1.590s 80.443us 1 1 100.00
hmac_long_msg 58.250s 7.235ms 1 1 100.00
hmac_back_pressure 58.850s 5.370ms 1 1 100.00
hmac_datapath_stress 4.958m 2.508ms 1 1 100.00
hmac_burst_wr 20.180s 4.506ms 1 1 100.00
hmac_error 1.333m 36.499ms 1 1 100.00
hmac_wipe_secret 54.310s 9.401ms 1 1 100.00
hmac_test_sha256_vectors 9.190s 1.637ms 1 1 100.00
hmac_test_sha384_vectors 19.570s 229.298us 1 1 100.00
hmac_test_sha512_vectors 23.890s 466.932us 1 1 100.00
hmac_test_hmac256_vectors 8.060s 2.164ms 1 1 100.00
hmac_test_hmac384_vectors 10.840s 1.029ms 1 1 100.00
hmac_test_hmac512_vectors 9.790s 285.849us 1 1 100.00
hmac_stress_all 5.080s 115.049us 1 1 100.00
V2 stress_all hmac_stress_all 5.080s 115.049us 1 1 100.00
V2 alert_test hmac_alert_test 1.520s 12.426us 1 1 100.00
V2 intr_test hmac_intr_test 1.430s 14.987us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.150s 69.574us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.150s 69.574us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.600s 44.575us 1 1 100.00
hmac_csr_rw 1.870s 54.326us 1 1 100.00
hmac_csr_aliasing 6.610s 2.928ms 1 1 100.00
hmac_same_csr_outstanding 2.930s 168.069us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.600s 44.575us 1 1 100.00
hmac_csr_rw 1.870s 54.326us 1 1 100.00
hmac_csr_aliasing 6.610s 2.928ms 1 1 100.00
hmac_same_csr_outstanding 2.930s 168.069us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.980s 75.267us 1 1 100.00
hmac_tl_intg_err 3.470s 345.070us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.470s 345.070us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 1.590s 80.443us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.310s 80.981us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 32.620s 14.164ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 6.930s 398.036us 1 1 100.00
TOTAL 28 28 100.00