I2C Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	37.470s	1.748ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.640s	1.194ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.520s	57.822us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.600s	29.445us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.250s	1.586ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.970s	28.938us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.740s	42.245us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.600s	29.445us	1	1	100.00
		i2c_csr_aliasing	1.970s	28.938us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	7.390s	1.360ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	5.653m	58.155ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	14.248m	49.558ms	1	1	100.00
V2	host_override	i2c_host_override	1.510s	34.096us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.258m	3.460ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	26.360s	1.332ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.970s	261.538us	1	1	100.00
		i2c_host_fifo_fmt_empty	2.980s	163.983us	1	1	100.00
		i2c_host_fifo_reset_rx	4.440s	203.205us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	38.950s	2.694ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.690s	3.727ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.490s	163.535us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.080s	19.767ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	21.410s	6.254ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.950s	1.175ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	34.210s	4.576ms	1	1	100.00
		i2c_target_intr_smoke	5.900s	4.973ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.120s	152.123us	1	1	100.00
		i2c_target_fifo_reset_tx	2.260s	201.763us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	30.770s	35.517ms	1	1	100.00
		i2c_target_stress_rd	34.210s	4.576ms	1	1	100.00
		i2c_target_intr_stress_wr	11.290s	7.079ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.310s	5.847ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	43.730s	5.209ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.660s	486.708us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	10.110s	10.203ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.750s	568.326us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.130s	593.327us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	14.248m	49.558ms	1	1	100.00
		i2c_host_perf_precise	1.850s	382.739us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.690s	3.727ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.420s	52.950us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.880s	967.611us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.710s	1.003ms	1	1	100.00
		i2c_target_nack_txstretch	1.970s	458.737us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.270s	1.749ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.540s	547.287us	1	1	100.00
V2	alert_test	i2c_alert_test	1.440s	19.186us	1	1	100.00
V2	intr_test	i2c_intr_test	1.430s	28.119us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.590s	411.408us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.590s	411.408us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.520s	57.822us	1	1	100.00
		i2c_csr_rw	1.600s	29.445us	1	1	100.00
		i2c_csr_aliasing	1.970s	28.938us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	32.735us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.520s	57.822us	1	1	100.00
		i2c_csr_rw	1.600s	29.445us	1	1	100.00
		i2c_csr_aliasing	1.970s	28.938us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	32.735us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	1.980s	76.587us	1	1	100.00
		i2c_sec_cm	1.710s	579.365us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.980s	76.587us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	38.010s	4.188ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.950s	463.505us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	26.730s	4.286ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.11921562437173382370434835757745987118491068183542836877802026287908290809940
      Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4188290537 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4188290537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.35583713783151443588439604277275116054530939824905336558491121642313498106911
      Line 105, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4285780669 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4285780669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.72442002135360220021619577491040722828691594317863278315324357208538355002042
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 463504793 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 463504793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.92860390789278453450177982617633462966212745640565329708541254008028086503489
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10202501909 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10202501909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.21865722122234517927335698793423153269281776160178468857427279646688960266319
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 163535330 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x56dc9414, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 163535330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---