KEYMGR Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.610s	221.030us	1	1	100.00
V1	random	keymgr_random	2.950s	46.260us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.810s	58.793us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.740s	64.279us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.290s	930.455us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.870s	128.979us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.520s	120.627us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.740s	64.279us	1	1	100.00
		keymgr_csr_aliasing	3.870s	128.979us	0	1	0.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.640s	235.559us	1	1	100.00
V2	sideload	keymgr_sideload	4.200s	526.188us	1	1	100.00
		keymgr_sideload_kmac	3.220s	137.149us	1	1	100.00
		keymgr_sideload_aes	3.090s	98.608us	1	1	100.00
		keymgr_sideload_otbn	14.560s	1.106ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	4.780s	464.300us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.390s	49.948us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.210s	218.767us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.840s	689.373us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.200s	91.933us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.190s	199.951us	1	1	100.00
V2	stress_all	keymgr_stress_all	12.550s	379.881us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.660s	144.228us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.650s	32.559us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.380s	244.311us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.380s	244.311us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.810s	58.793us	1	1	100.00
		keymgr_csr_rw	1.740s	64.279us	1	1	100.00
		keymgr_csr_aliasing	3.870s	128.979us	0	1	0.00
		keymgr_same_csr_outstanding	2.160s	55.512us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.810s	58.793us	1	1	100.00
		keymgr_csr_rw	1.740s	64.279us	1	1	100.00
		keymgr_csr_aliasing	3.870s	128.979us	0	1	0.00
		keymgr_same_csr_outstanding	2.160s	55.512us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
		keymgr_tl_intg_err	7.080s	824.279us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.150s	716.975us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.150s	716.975us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.150s	716.975us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.150s	716.975us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	7.670s	791.285us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.080s	824.279us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.150s	716.975us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.640s	235.559us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.950s	46.260us	1	1	100.00
		keymgr_csr_rw	1.740s	64.279us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.950s	46.260us	1	1	100.00
		keymgr_csr_rw	1.740s	64.279us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.950s	46.260us	1	1	100.00
		keymgr_csr_rw	1.740s	64.279us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.390s	49.948us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.200s	91.933us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.200s	91.933us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.950s	46.260us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	4.940s	210.469us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.390s	460.138us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.390s	49.948us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.390s	460.138us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.390s	460.138us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.390s	460.138us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.780s	6.120ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.390s	460.138us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.960s	1.591ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.4216096053403217067501877988848926474050996086723933648832030035333089531471
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @ 930454758 ps: (keymgr_csr_assert_fpv.sv:442) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @ 930454758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.36845850122149385301652928074950408997803367724993619732066100220962502289455
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
        UVM_ERROR @ 128978587 ps: (keymgr_csr_assert_fpv.sv:490) [ASSERT FAILED] attest_sw_binding_7_rd_A
        UVM_INFO @ 128978587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---