| V1 |
smoke |
keymgr_dpe_smoke |
11.760s |
757.159us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.880s |
24.890us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
2.450s |
87.997us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
15.830s |
3.700ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
4.170s |
430.812us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
2.310s |
91.512us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
2.450s |
87.997us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.170s |
430.812us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.760s |
14.746us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
2.190s |
107.791us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.990s |
254.429us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.990s |
254.429us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.880s |
24.890us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.450s |
87.997us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.170s |
430.812us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
3.020s |
82.043us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.880s |
24.890us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.450s |
87.997us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.170s |
430.812us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
3.020s |
82.043us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
7.330s |
1.247ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
4.110s |
99.684us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
3.080s |
473.771us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
3.080s |
473.771us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
3.080s |
473.771us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
3.080s |
473.771us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
4.640s |
171.360us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
7.330s |
1.247ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
7.330s |
1.247ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |