KMAC/MASKED Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	44.540s	9.097ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.810s	20.960us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.980s	41.422us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.260s	4.006ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.360s	233.694us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.470s	128.128us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.980s	41.422us	1	1	100.00
		kmac_csr_aliasing	4.360s	233.694us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.600s	11.271us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.880s	19.748us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	17.231m	52.270ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.216m	17.244ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.120m	37.634ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.850m	154.844ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.858m	44.165ms	1	1	100.00
		kmac_test_vectors_sha3_512	18.090s	2.422ms	1	1	100.00
		kmac_test_vectors_shake_128	2.400m	7.648ms	1	1	100.00
		kmac_test_vectors_shake_256	1.484m	10.787ms	1	1	100.00
		kmac_test_vectors_kmac	3.180s	88.324us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.130s	41.948us	1	1	100.00
V2	sideload	kmac_sideload	4.862m	59.598ms	1	1	100.00
V2	app	kmac_app	37.460s	7.910ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.346m	20.646ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.300m	13.093ms	1	1	100.00
V2	error	kmac_error	45.620s	3.046ms	1	1	100.00
V2	key_error	kmac_key_error	8.350s	979.871us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.820s	147.658us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.990s	60.996us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.190s	83.036us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.530s	9.047ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.490s	59.387us	1	1	100.00
V2	stress_all	kmac_stress_all	12.394m	58.653ms	0	1	0.00
V2	intr_test	kmac_intr_test	1.750s	18.795us	1	1	100.00
V2	alert_test	kmac_alert_test	1.920s	65.423us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.190s	239.680us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.190s	239.680us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.810s	20.960us	1	1	100.00
		kmac_csr_rw	1.980s	41.422us	1	1	100.00
		kmac_csr_aliasing	4.360s	233.694us	1	1	100.00
		kmac_same_csr_outstanding	2.310s	61.070us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.810s	20.960us	1	1	100.00
		kmac_csr_rw	1.980s	41.422us	1	1	100.00
		kmac_csr_aliasing	4.360s	233.694us	1	1	100.00
		kmac_same_csr_outstanding	2.310s	61.070us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.840s	86.476us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.840s	86.476us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.840s	86.476us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.840s	86.476us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.810s	32.590us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	35.170s	11.558ms	1	1	100.00
		kmac_tl_intg_err	2.760s	221.982us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.760s	221.982us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.490s	59.387us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	44.540s	9.097ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.862m	59.598ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.840s	86.476us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	35.170s	11.558ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	35.170s	11.558ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	35.170s	11.558ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	44.540s	9.097ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.490s	59.387us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	35.170s	11.558ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.495m	8.180ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	44.540s	9.097ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	15.900s	2.048ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 0.kmac_stress_all.58229700008436389580930941970396195314736443403407647235589173839004437062926
      Line 307, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log

        UVM_ERROR @ 58653206861 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 58653206861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.77957855323167092721499246649824527075430763253752050316027705008384999720034
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  32589738 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  32589738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---