KMAC/UNMASKED Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	8.420s	637.416us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.970s	27.807us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.660s	60.353us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.170s	578.427us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.520s	545.743us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.130s	42.583us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.660s	60.353us	1	1	100.00
		kmac_csr_aliasing	7.520s	545.743us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.660s	11.487us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.060s	39.298us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.321m	16.065ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.403m	86.142ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.587m	62.958ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.340s	1.373ms	1	1	100.00
		kmac_test_vectors_sha3_384	12.638m	14.099ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.411m	9.295ms	1	1	100.00
		kmac_test_vectors_shake_128	2.534m	57.056ms	1	1	100.00
		kmac_test_vectors_shake_256	16.076m	160.638ms	1	1	100.00
		kmac_test_vectors_kmac	2.310s	114.641us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.390s	96.264us	1	1	100.00
V2	sideload	kmac_sideload	3.057m	27.063ms	1	1	100.00
V2	app	kmac_app	1.891m	14.663ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.403m	5.190ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.447m	31.863ms	1	1	100.00
V2	error	kmac_error	19.510s	2.739ms	1	1	100.00
V2	key_error	kmac_key_error	4.930s	2.242ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	23.530s	10.802ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	14.590s	286.779us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.870s	4.507ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	6.320s	2.001ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	15.820s	1.075ms	1	1	100.00
V2	stress_all	kmac_stress_all	13.131m	28.476ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.710s	57.188us	1	1	100.00
V2	alert_test	kmac_alert_test	1.780s	17.471us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.600s	80.945us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.600s	80.945us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.970s	27.807us	1	1	100.00
		kmac_csr_rw	1.660s	60.353us	1	1	100.00
		kmac_csr_aliasing	7.520s	545.743us	1	1	100.00
		kmac_same_csr_outstanding	2.310s	236.255us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.970s	27.807us	1	1	100.00
		kmac_csr_rw	1.660s	60.353us	1	1	100.00
		kmac_csr_aliasing	7.520s	545.743us	1	1	100.00
		kmac_same_csr_outstanding	2.310s	236.255us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.110s	44.270us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.110s	44.270us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.110s	44.270us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.110s	44.270us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.790s	12.349us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	23.350s	8.401ms	1	1	100.00
		kmac_tl_intg_err	3.050s	127.108us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.050s	127.108us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	15.820s	1.075ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	8.420s	637.416us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.057m	27.063ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.110s	44.270us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	23.350s	8.401ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	23.350s	8.401ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	23.350s	8.401ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	8.420s	637.416us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	15.820s	1.075ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	23.350s	8.401ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.800m	2.406ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	8.420s	637.416us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.458m	6.564ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.38127654882676627875877062246494300924423280880273804821338833730322293559893
      Line 99, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10801778880 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x70300000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
        UVM_INFO @ 10801778880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.73705077628609088700348951757424170361818292711901358140423939471858366388996
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @  12348786 ps: (kmac_csr_assert_fpv.sv:506) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @  12348786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---