4ec736f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 40.000s | 5.046ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 8.000s | 35.263us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 11.913us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 36.632us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 10.417us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 943.777ns | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 11.913us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 10.417us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 12.000s | 874.562us | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 32.000s | 2.667ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 1.383m | 8.312ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 22.801us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 11.000s | 6.532us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 11.000s | 6.532us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 8.000s | 35.263us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 11.913us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 10.417us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 20.710us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 8.000s | 35.263us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 11.913us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 10.417us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 20.710us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 17.151us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 8.000s | 32.640us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.102722306886153069263744504887218154803601913561052193576192127149808125575206
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 6532365 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x3a796c64 a_data = 0xa6889122 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xad a_opcode = Get a_user = 0x235a7 d_data = 0x96502160 d_size = 0x2 d_param = 0x0 d_source = 0x45 d_opcode = AccessAckData d_error = 0 d_user = 11100111010100 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 6532365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.74691637481931221539948930777168813177851891721281158910673063572256802300117
Line 88, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 32639950 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xfdf6c254 a_data = 0x94c6a042 a_mask = 0x7 a_size = 0x2 a_param = 0x0 a_source = 0xfb a_opcode = Get a_user = 0x24ef6 d_data = 0xa5b0001d d_size = 0x2 d_param = 0x0 d_source = 0x57 d_opcode = AccessAck d_error = 0 d_user = 11001010001101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 32639950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.102583848957083133104168620181280017719994157566623352018955796845416586449684
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 943777 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xf04b94d4 a_data = 0xa17d0b68 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xc6 a_opcode = PutPartialData a_user = 0x1b3a1 d_data = 0x9c7e136f d_size = 0x0 d_param = 0x0 d_source = 0x7f d_opcode = AccessAckData d_error = 0 d_user = 10111110010111 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 943777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---