ROM_CTRL/64KB Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.450s 1.775ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.800s 298.783us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.290s 2.509ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.850s 208.226us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.900s 543.864us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.510s 832.441us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.290s 2.509ms 1 1 100.00
rom_ctrl_csr_aliasing 6.900s 543.864us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.100s 1.073ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.380s 205.434us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.210s 247.087us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 19.810s 1.106ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.700s 1.369ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 9.180s 299.389us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.690s 554.274us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.690s 554.274us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.800s 298.783us 1 1 100.00
rom_ctrl_csr_rw 7.290s 2.509ms 1 1 100.00
rom_ctrl_csr_aliasing 6.900s 543.864us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.070s 1.089ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.800s 298.783us 1 1 100.00
rom_ctrl_csr_rw 7.290s 2.509ms 1 1 100.00
rom_ctrl_csr_aliasing 6.900s 543.864us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.070s 1.089ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 24.510s 4.439ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.737m 1.507ms 1 1 100.00
rom_ctrl_tl_intg_err 1.078m 449.540us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.737m 1.507ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.737m 1.507ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.737m 1.507ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.737m 1.507ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.450s 1.775ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.450s 1.775ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.450s 1.775ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.078m 449.540us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.700s 1.369ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.933m 18.724ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 24.510s 4.439ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.737m 1.507ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.003m 3.251ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00