| V1 |
random |
rv_timer_random |
1.680s |
16.413us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.830s |
14.181us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.420s |
21.591us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.240s |
123.114us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.620s |
17.913us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.700s |
21.121us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.420s |
21.591us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.620s |
17.913us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.400s |
107.865us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.610s |
39.433us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
6.590s |
12.952ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
6.590s |
12.952ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
5.910s |
2.827ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.580s |
21.416us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.690s |
14.981us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.330s |
261.427us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.330s |
261.427us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.830s |
14.181us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.420s |
21.591us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.620s |
17.913us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.670s |
30.823us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.830s |
14.181us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.420s |
21.591us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.620s |
17.913us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.670s |
30.823us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.700s |
488.709us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.910s |
51.076us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.910s |
51.076us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.570s |
45.181us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.570s |
30.514us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
41.010s |
6.620ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |