SPI_DEVICE/1R1W Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.048m	18.372ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	81.103us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	97.967us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.860s	4.848ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.680s	964.224us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.750s	109.196us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	97.967us	1	1	100.00
		spi_device_csr_aliasing	16.680s	964.224us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.660s	10.803us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.620s	116.501us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.730s	56.825us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.540s	908.326ns	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.500s	10.904us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.770s	34.877us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.770s	34.877us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.580s	22.505us	1	1	100.00
		spi_device_tpm_sts_read	1.610s	76.327us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.570s	1.881ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.700s	1.822ms	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.900s	315.521us	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.900s	315.521us	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	21.700s	2.789ms	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	21.700s	2.789ms	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.700s	2.789ms	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	21.700s	2.789ms	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.700s	2.789ms	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.080s	516.372us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	43.110s	30.923ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	43.110s	30.923ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	43.110s	30.923ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	21.220s	2.104ms	1	1	100.00
		spi_device_read_buffer_direct	5.000s	193.321us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	43.110s	30.923ms	1	1	100.00
		spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.444m	133.522ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.780s	146.946us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.780s	146.946us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.048m	18.372ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	26.900s	2.789ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.260m	31.611ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.520s	43.670us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.940s	22.565us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.550s	165.876us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.550s	165.876us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	81.103us	1	1	100.00
		spi_device_csr_rw	2.880s	97.967us	1	1	100.00
		spi_device_csr_aliasing	16.680s	964.224us	1	1	100.00
		spi_device_same_csr_outstanding	3.390s	642.441us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	81.103us	1	1	100.00
		spi_device_csr_rw	2.880s	97.967us	1	1	100.00
		spi_device_csr_aliasing	16.680s	964.224us	1	1	100.00
		spi_device_same_csr_outstanding	3.390s	642.441us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.100s	319.422us	1	1	100.00
		spi_device_tl_intg_err	6.630s	106.018us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.630s	106.018us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	56.960s	28.572ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.67658341381855857248657400863412342674000199078363479253153449215577855194250
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    803326 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[100])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    803326 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    803326 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[996])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.101116715438957051025190319163391571141324735701972506005407056610570379144518
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   8085703 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x36cf06 [1101101100111100000110] vs 0x0 [0])
        UVM_ERROR @   8119703 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x480d48 [10010000000110101001000] vs 0x0 [0])
        UVM_ERROR @   8219703 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4f6bd9 [10011110110101111011001] vs 0x0 [0])
        UVM_ERROR @   8284703 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6aee0a [11010101110111000001010] vs 0x0 [0])
        UVM_ERROR @   8298703 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x41709 [1000001011100001001] vs 0x0 [0])