SPI_HOST Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	18.000s	1.372ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	50.085us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	41.562us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	1.155ms	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	87.392us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	25.993us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	41.562us	1	1	100.00
		spi_host_csr_aliasing	4.000s	87.392us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	16.401us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	59.693us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	26.023us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	52.132us	1	1	100.00
		spi_host_error_cmd	4.000s	88.680us	1	1	100.00
		spi_host_event	11.000s	1.899ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	95.835us	1	1	100.00
V2	speed	spi_host_speed	4.000s	95.835us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	95.835us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	118.231us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	32.447us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	95.835us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	95.835us	1	1	100.00
V2	duplex	spi_host_smoke	18.000s	1.372ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	18.000s	1.372ms	1	1	100.00
V2	stress_all	spi_host_stress_all	12.000s	827.041us	1	1	100.00
V2	spien	spi_host_spien	10.000s	480.291us	1	1	100.00
V2	stall	spi_host_status_stall	23.000s	2.152ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	372.836us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	52.132us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	17.909us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	28.313us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	170.612us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	170.612us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	50.085us	1	1	100.00
		spi_host_csr_rw	3.000s	41.562us	1	1	100.00
		spi_host_csr_aliasing	4.000s	87.392us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	60.968us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	50.085us	1	1	100.00
		spi_host_csr_rw	3.000s	41.562us	1	1	100.00
		spi_host_csr_aliasing	4.000s	87.392us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	60.968us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	440.539us	1	1	100.00
		spi_host_sec_cm	3.000s	189.225us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	440.539us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.750m	9.466ms	1	1	100.00
		TOTAL			26	26	100.00