SRAM_CTRL/MAIN Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	17.820s	8.034ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.630s	51.908us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	39.845us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.620s	311.187us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.780s	25.467us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.310s	1.905ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	39.845us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	25.467us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.051m	4.108ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.074m	23.193ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	15.022m	310.784ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.044m	19.316ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.108m	103.749ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.969m	50.252ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	25.360s	14.936ms	1	1	100.00
V2	executable	sram_ctrl_executable	13.716m	132.063ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	24.760s	909.419us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.472m	11.618ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	22.470s	3.132ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.450s	1.443ms	1	1	100.00
		sram_ctrl_throughput_w_readback	15.880s	2.977ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.859m	1.451ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.390s	357.985us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	9.243m	100.328ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.600s	43.338us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.880s	39.694us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.880s	39.694us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.630s	51.908us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	39.845us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	25.467us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	17.950us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.630s	51.908us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	39.845us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	25.467us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	17.950us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	32.460s	35.210ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.590s	15.917us	0	1	0.00
		sram_ctrl_tl_intg_err	2.430s	362.859us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.590s	15.917us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.430s	362.859us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.859m	1.451ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.859m	1.451ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	39.845us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	13.716m	132.063ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	13.716m	132.063ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	13.716m	132.063ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	25.360s	14.936ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.870s	2.780ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	32.460s	35.210ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.550s	1.446ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	17.820s	8.034ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	17.820s	8.034ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	13.716m	132.063ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.590s	15.917us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	25.360s	14.936ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.590s	15.917us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.590s	15.917us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	17.820s	8.034ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.590s	15.917us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	44.120s	4.453ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.1521486360697609972613858845069187461330135098739735245915318486129459461491
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1446414214 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0xe)
        UVM_INFO @ 1446414214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.30252142025729075441979779754753806718982841336330014712182360823754614868534
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  15917413 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  15917413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---