SRAM_CTRL/RET Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.290s	354.907us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.660s	32.724us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.640s	26.248us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.560s	98.748us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	23.926us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.600s	36.280us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.640s	26.248us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	23.926us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.640s	130.815us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.400s	272.825us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.653m	149.229ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.064m	14.331ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.670s	3.515ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.449m	4.690ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.590s	552.745us	1	1	100.00
V2	executable	sram_ctrl_executable	16.840m	25.552ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	22.510s	390.555us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.378m	5.415ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	10.100s	304.497us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	48.800s	787.058us	1	1	100.00
		sram_ctrl_throughput_w_readback	31.820s	2.095ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.521m	24.198ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.760s	65.454us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	12.475m	99.198ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.680s	16.695us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.710s	78.751us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.710s	78.751us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.660s	32.724us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	26.248us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	23.926us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	51.598us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.660s	32.724us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	26.248us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	23.926us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	51.598us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.680s	1.347ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.690s	26.258us	0	1	0.00
		sram_ctrl_tl_intg_err	2.240s	121.377us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.690s	26.258us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.240s	121.377us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.521m	24.198ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.521m	24.198ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.640s	26.248us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.840m	25.552ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.840m	25.552ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.840m	25.552ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.590s	552.745us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.060s	41.829us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.680s	1.347ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.680s	209.133us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.290s	354.907us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.290s	354.907us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.840m	25.552ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.690s	26.258us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.590s	552.745us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.690s	26.258us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.690s	26.258us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.290s	354.907us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.690s	26.258us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.434m	18.826ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.73105313733491530866507470245511115991893510063406945802914309382159234524134
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  26258113 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  26258113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---