UART Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.880s	6.050ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.500s	39.340us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.520s	80.403us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.660s	56.918us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.520s	54.108us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.600s	46.316us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.520s	80.403us	1	1	100.00
		uart_csr_aliasing	1.520s	54.108us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	7.740s	6.463ms	1	1	100.00
V2	parity	uart_smoke	7.880s	6.050ms	1	1	100.00
		uart_tx_rx	7.740s	6.463ms	1	1	100.00
V2	parity_error	uart_intr	9.700s	23.473ms	1	1	100.00
		uart_rx_parity_err	18.410s	32.935ms	1	1	100.00
V2	watermark	uart_tx_rx	7.740s	6.463ms	1	1	100.00
		uart_intr	9.700s	23.473ms	1	1	100.00
V2	fifo_full	uart_fifo_full	4.172m	118.317ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	47.660s	179.641ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	4.770s	26.994ms	1	1	100.00
V2	rx_frame_err	uart_intr	9.700s	23.473ms	1	1	100.00
V2	rx_break_err	uart_intr	9.700s	23.473ms	1	1	100.00
V2	rx_timeout	uart_intr	9.700s	23.473ms	1	1	100.00
V2	perf	uart_perf	2.192m	17.887ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.750s	5.983ms	1	1	100.00
V2	line_loopback	uart_loopback	6.750s	5.983ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.520s	101.795us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.660s	4.108ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.500s	1.270ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	26.740s	6.702ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.644m	137.584ms	1	1	100.00
V2	stress_all	uart_stress_all	5.755m	173.691ms	0	1	0.00
V2	alert_test	uart_alert_test	1.450s	21.782us	1	1	100.00
V2	intr_test	uart_intr_test	1.590s	31.144us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.550s	552.298us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.550s	552.298us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.500s	39.340us	1	1	100.00
		uart_csr_rw	1.520s	80.403us	1	1	100.00
		uart_csr_aliasing	1.520s	54.108us	1	1	100.00
		uart_same_csr_outstanding	1.560s	20.904us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.500s	39.340us	1	1	100.00
		uart_csr_rw	1.520s	80.403us	1	1	100.00
		uart_csr_aliasing	1.520s	54.108us	1	1	100.00
		uart_same_csr_outstanding	1.560s	20.904us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.710s	129.298us	1	1	100.00
		uart_tl_intg_err	1.730s	92.388us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.730s	92.388us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	29.700s	3.127ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.42676203565465169550912506293547165501431965188837686589266771653193821429877
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  59876674 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  61488906 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  63652154 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  72754122 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  81998946 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.48994054428743320241254740992299691453120383684524840710651737416846022304406
      Line 80, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 169660669315 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 170320411435 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 170320464067 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 170320516699 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (177 [0xb1] vs 252 [0xfc]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 170408833195 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0