CHIP Simulation Results

Thursday June 12 2025 17:08:19 UTC

GitHub Revision: `4ec736f`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.486m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.486m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	4.060m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.115m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.541m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.296m	5.034ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.296m	5.034ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.296m	5.034ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	26.800s	10.320us	0	1	0.00
		chip_sw_example_manufacturer	5.045m		0	1	0.00
		chip_sw_example_concurrency	3.900m	5.016ms	1	1	100.00
		chip_sw_uart_smoketest_signed	10.977s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.160s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.420s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.420s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.830s	13.103us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	4.437m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.362m	8.367ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.775m	5.665ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.378m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.987m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	3.507m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.215m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.940s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.940s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.777m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.180m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.961m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.961m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.626m	4.301ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.618m	5.324ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.538m	14.288ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.980s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.624s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.601m	23.825ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.659m	5.291ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.452m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.452m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	50.086s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.635m	5.491ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.635m	5.491ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.097m	18.024ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.716m	4.130ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.387m	3.814ms	1	1	100.00
		chip_sw_aes_idle	3.511m	4.783ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.132m	5.897ms	1	1	100.00
		chip_sw_kmac_idle	3.542m	5.126ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.069m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.656m	11.823ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	11.269m	12.026ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.319m	12.019ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.061s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.694s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.000s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.542s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.851s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.639s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.204s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.061s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.694s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.000s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.542s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.851s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.639s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.204s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.598s		0	1	0.00
		chip_sw_aes_enc_jitter_en	56.340s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.240s	10.300us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.380s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.460s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.845s		0	1	0.00
		chip_sw_clkmgr_jitter	3.694m	4.160ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.340m	4.257ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	14.887s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	34.190s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	33.480s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	34.800s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	33.730s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	39.490s	10.120us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	10.924s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.062s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.163s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.224s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.360m	13.730ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.753m	11.912ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.635m	5.491ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	21.492s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.753m	11.912ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.689s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	38.170s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	36.749s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	1.279m		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.150m		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.360m	13.730ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.538m	14.288ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.092m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.996m	8.313ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.563m	9.990ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.643m	4.309ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.360m	13.730ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.227s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.591s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.360m	13.730ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	16.764s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.563m	9.990ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.369s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.982s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.163s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.128s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.146s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.057s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.591s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.321m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.355m	9.969ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.437m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.556m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.990m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	37.977s		0	1	0.00
		chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.404m	7.454ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.421m	12.352ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.292s		0	1	0.00
		chip_prim_tl_access	4.053m	5.432ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.061s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.694s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.000s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.542s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.851s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.639s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.204s		0	1	0.00
		chip_rv_dm_lc_disabled	12.601m	23.825ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.554m	4.805ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	56.340s	10.260us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.988m	5.263ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.511m	4.783ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.905m	4.653ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	35.240s	10.300us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.132m	5.897ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.990m	5.424ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.656m	5.783ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	35.460s	10.340us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.404m	7.454ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.840s	10.320us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.571m	4.256ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.542m	5.126ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.102s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.102s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.977s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.933m	5.024ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.456s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.404m	7.454ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.380s	10.140us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.250s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.598s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.387m	3.814ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.387m	3.814ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.387m	3.814ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.911m	5.731ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.421m	12.352ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.421m	12.352ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.325m	8.071ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.845s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.292s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.360m	13.730ms	1	1	100.00
		chip_sw_data_integrity_escalation	4.961m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.911m	5.731ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.404m	7.454ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.325m	8.071ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.381m	4.635ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.911m	5.731ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.404m	7.454ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.325m	8.071ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.381m	4.635ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.686s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.321m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.437m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.556m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.990m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	37.977s		0	1	0.00
		chip_sw_lc_ctrl_transition	28.708s		0	1	0.00
		chip_prim_tl_access	4.053m	5.432ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.053m	5.432ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	17.929s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	10.658s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.062s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.598s		0	1	0.00
		chip_sw_aes_enc_jitter_en	56.340s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.240s	10.300us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.380s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.460s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.845s		0	1	0.00
		chip_sw_clkmgr_jitter	3.694m	4.160ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.998m	10.508ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.998m	10.508ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.321m	5.937ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.219m	3.337ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.525m	4.914ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.732m	4.940ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.755m	4.302ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.283m	5.195ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.381m	4.635ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.092m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.092m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.810m	5.673ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.388m	4.438ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.316m	4.964ms	1	1	100.00
		chip_sw_csrng_smoketest	2.932m	5.512ms	1	1	100.00
		chip_sw_gpio_smoketest	4.229m	5.649ms	1	1	100.00
		chip_sw_hmac_smoketest	3.950m	5.885ms	1	1	100.00
		chip_sw_kmac_smoketest	3.788m	3.958ms	1	1	100.00
		chip_sw_otbn_smoketest	4.399m	5.629ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.207m	4.908ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.654m	4.547ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.479m	4.726ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.127m	3.426ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.259m	4.138ms	1	1	100.00
		chip_sw_uart_smoketest	3.233m	5.982ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	17.356s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.977s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.437m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.314s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.016m	5.348ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.734m	4.711ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.832m	4.376ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.529m	4.552ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	16.277s		0	1	0.00
		chip_rv_dm_lc_disabled	12.601m	23.825ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	35.480s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.182s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.898s		0	1	0.00
		chip_sw_lc_walkthrough_rma	32.072s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	16.277s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.417s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.466s		0	1	0.00
		rom_volatile_raw_unlock	11.439s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.669s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	4.376m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	4.492m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.999m	3.720ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.999m	3.720ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.420s		0	1	0.00
		chip_same_csr_outstanding	7.930s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.420s		0	1	0.00
		chip_same_csr_outstanding	7.930s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	35.080s	76.266us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	10.040s	11.532us	1	1	100.00
		xbar_smoke_large_delays	4.837m	2.697ms	1	1	100.00
		xbar_smoke_slow_rsp	4.717m	1.925ms	1	1	100.00
		xbar_random_zero_delays	1.060m	53.322us	1	1	100.00
		xbar_random_large_delays	13.245m	7.196ms	1	1	100.00
		xbar_random_slow_rsp	20.094m	7.602ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	37.050s	67.176us	1	1	100.00
		xbar_error_and_unmapped_addr	30.530s	24.861us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	25.210s	37.348us	1	1	100.00
		xbar_error_and_unmapped_addr	30.530s	24.861us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.685m	701.552us	1	1	100.00
		xbar_access_same_device_slow_rsp	42.595m	17.131ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	53.010s	50.353us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	36.520s	29.612us	1	1	100.00
		xbar_stress_all_with_error	11.279m	2.322ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	9.536m	539.466us	1	1	100.00
		xbar_stress_all_with_reset_error	20.599m	1.765ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.167s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.098s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.076s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.642s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.928s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.019s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.347s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.777s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.844s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.882s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.638s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.381s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.820s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.695s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.533s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	15.213s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.010s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.948s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.723s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.108s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.945s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.556s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.693s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.507s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.652s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.575s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.483s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.683s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	14.952s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.605s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.959s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.260s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.975s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.463s		0	1	0.00
		rom_e2e_asm_init_dev	13.096s		0	1	0.00
		rom_e2e_asm_init_prod	12.291s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.484s		0	1	0.00
		rom_e2e_asm_init_rma	11.284s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.327s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.339s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.526s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.946s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.977m	3.625ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	46.320s	1.558ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.999s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.789s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.018s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.241s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.360m	13.730ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	10.774s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.727m	12.186ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.334s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.736s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.999s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.789s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.018s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.589s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.015s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.209s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.080m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.428m	14.157ms	1	1	100.00
		chip_plic_all_irqs_0	8.315m	6.269ms	1	1	100.00
		chip_plic_all_irqs_10	8.744m	6.256ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.893m	5.283ms	1	1	100.00
		chip_sw_dma_abort	4.430m	5.424ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.826s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.319s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.552s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.623s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.891s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.943s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.815s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.866s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.907s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.171s		0	1	0.00
		chip_sw_mbx_smoketest	3.544m	4.064ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.56380307080872391547840678498663332485387182311313441310434169452725517343051
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (cfb03c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 283.278s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.24706916968238791893314147276967749713162440378017566167694608790404492816509
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (53e6ce)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 286.313s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.94070410970806317742642692385118569782687410152889605826514792586950290516755
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (70ff6b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 275.862s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.89303892375035055896421246401242204649997679108484070592332066841585497621245
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (3f4a76)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 360.301s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.50898794479958110166255991958555763818594325295550884921339672849596548934142
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (f30a11)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 259.142s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.106620896547131384602226530827358270482527049157412322852341483773355751909770
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.41303196502799704025444185117059808889783953092358170204996923558419650885065
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.9838106787339211068346697311935212292095970006625589893120500302238045337890
    Line 413, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.96757435941927806627278070809968957025385194951494670107860936846822138161633
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.83259282787791532676937917342626492527578876250740795229223204309508507729580
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.100640122568459677111563583371095863465344454555304799315500712136982341400284
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.112143767610835635739684428451645558860362188504557086414017683577575552353352
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.70135196880460109364918278376221621145264318794859187832808401950813765753458
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.36456324037705206451494513840679661716765271828692384557267477924115137634347
Line 570, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.853586 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.853586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.54395320716474821858422112300400420398632438269862673523277605210989230201614
Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18019.391794 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18019.391794 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.10934338637034555653506791482839946139341355020123850612616272138703408165503
Line 497, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18023.738152 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18023.738152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.91076309874053249553090366770468856221829034035378590599098191206533321598625
Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12019.361888 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12019.361888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.26950548098999343213403536713760284981595747004153220849404527958692021448395
Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12026.223234 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.223234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.30455944807658511575061176151388950440434950078443410884078278740623405441946
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12019.203044 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12019.203044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.92520815918853568919218570988607445875619138353733700551885984214879289543955
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7454.133754 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (109697492034967261299064396990556281714508293482511003418447945591122747181209 [0xf2869489b5fa4114f9a4eb862a0ddec675ff2546c9067ccec02d597f01f7c899] vs 45189844803335412857293276749085150995009203314330671031426582540492251217114 [0x63e88bb6ee715b7c8eeb80b2b3e89911af203e147d8038f40b40a214d4b23cda])
  UVM_INFO @ 7454.133754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.44616189844907961686227351189487592258148601923415032028536272320235657662503
Line 469, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9969.297922 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (106291026410677508153759511950122912328862927265873617945817116677614108915129 [0xeafe96c940eea88285ae64dee4d854aa2e0c253d1ae72d2c5427256e71f7b5b9] vs 47168754776460017640195155018632954183415447809812647239949939607287017575238 [0x684891b15f01d72d3a24a6ec298d0c769b11903e6207818845c1817bcf211346])
  UVM_INFO @ 9969.297922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.30501004479877413930908033811806258938066346852321773324824803961620147310593
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4301.363919 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h1ad32c5d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h1  a_user: 'h2488b  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4301.363919 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.56291569274668927072982911504585952800480132145695620907346976926621730399823
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5323.858900 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hd771754c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h1  a_user: 'h248e7  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5323.858900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.34680817485452368497548778685789616893054894799593988340677391098916014112441
    Line 858, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.69052211362884150735422159767409919887076804177549749908656476080528447619911
    Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5664.654262 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5664.654262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.90715384851501792958661324754471148872093451421541795571153868546308354566554
    Line 707, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9990.426680 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9990.426680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.66536074796691795883342683535625472686977104919916780786450786648008340356429
    Line 535, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5936.548690 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5936.548690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.56962051825439077206890884723381485513779115071320821180692305449476506351213
    Line 496, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3337.042976 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3337.042976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.112577102103522538496130245789810192834336089532911943307419480269436506607666
    Line 495, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5490.697544 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5490.697544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.13641105123107408871097204097491914785498545416308434549460025764352557806616
    Line 483, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4940.045480 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4940.045480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.82142458332051885985223486446645213516363846792464162646735883211670817479646
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35744) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.68602415557975888235449600664954376139643427962043295340165864667340498580271
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3720.386020 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35744) { a_addr: 'h2210  a_data: 'hf6f344eb  a_mask: 'h2  a_size: 'h2  a_param: 'h0  a_source: 'hc2  a_opcode: 'h4  a_user: 'h2668b  d_param: 'h0  d_source: 'hc2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3720.386020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.3058810323246753846379976558265799321901758652597084221459958341080331893186
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14287.860684 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14287.860684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.114340505514358361976762498932484484969749074642892182552812969212345691436729
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.15071024650914008872995978516554180570997865560946092969774289947722764586713
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5423.621784 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5423.621784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```