DMA Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	1.115ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	269.220us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	317.908us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	69.379us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	41.697us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	581.055us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	2.382ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	41.911us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	41.697us	1	1	100.00
		dma_csr_aliasing	9.000s	2.382ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.083m	14.333ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.283m	30.310ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	22.333m	141.194ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	7.117m	43.931ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.283m	30.310ms	1	1	100.00
V2	dma_abort	dma_abort	10.000s	2.759ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.783m	24.902ms	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	12.755us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	84.363us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	84.363us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	69.379us	1	1	100.00
		dma_csr_rw	4.000s	41.697us	1	1	100.00
		dma_csr_aliasing	9.000s	2.382ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	68.738us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	69.379us	1	1	100.00
		dma_csr_rw	4.000s	41.697us	1	1	100.00
		dma_csr_aliasing	9.000s	2.382ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	68.738us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	21.000s	128.924us	1	1	100.00
		dma_generic_stress	7.117m	43.931ms	1	1	100.00
		dma_handshake_stress	1.283m	30.310ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	1.005ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.700m	18.821ms	1	1	100.00
		dma_longer_transfer	6.000s	254.751us	1	1	100.00
		TOTAL			21	21	100.00