EDN Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.160s	48.023us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.650s	21.085us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.680s	35.625us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.420s	524.982us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.910s	18.505us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.110s	67.633us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.680s	35.625us	1	1	100.00
		edn_csr_aliasing	1.910s	18.505us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.880s	170.334us	1	1	100.00
V2	csrng_commands	edn_genbits	1.880s	170.334us	1	1	100.00
V2	genbits	edn_genbits	1.880s	170.334us	1	1	100.00
V2	interrupts	edn_intr	1.850s	28.519us	1	1	100.00
V2	alerts	edn_alert	2.140s	76.347us	1	1	100.00
V2	errs	edn_err	2.070s	20.884us	1	1	100.00
V2	disable	edn_disable	1.680s	46.989us	1	1	100.00
		edn_disable_auto_req_mode	1.960s	135.989us	1	1	100.00
V2	stress_all	edn_stress_all	1.810s	87.475us	1	1	100.00
V2	intr_test	edn_intr_test	1.720s	60.891us	1	1	100.00
V2	alert_test	edn_alert_test	1.700s	17.263us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.550s	197.651us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.550s	197.651us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.650s	21.085us	1	1	100.00
		edn_csr_rw	1.680s	35.625us	1	1	100.00
		edn_csr_aliasing	1.910s	18.505us	1	1	100.00
		edn_same_csr_outstanding	1.940s	114.407us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.650s	21.085us	1	1	100.00
		edn_csr_rw	1.680s	35.625us	1	1	100.00
		edn_csr_aliasing	1.910s	18.505us	1	1	100.00
		edn_same_csr_outstanding	1.940s	114.407us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.770s	897.932us	1	1	100.00
		edn_tl_intg_err	2.090s	144.310us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.780s	32.438us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.140s	76.347us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.770s	897.932us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.770s	897.932us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.770s	897.932us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.770s	897.932us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.140s	76.347us	1	1	100.00
		edn_sec_cm	6.770s	897.932us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.140s	76.347us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.090s	144.310us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	47.080s	6.408ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00