HMAC Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 1.640s 17.579us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.590s 21.969us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.570s 21.076us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.730s 4.407ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.880s 623.282us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.950s 118.516us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.570s 21.076us 1 1 100.00
hmac_csr_aliasing 4.880s 623.282us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.038m 10.904ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.007m 6.173ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.000m 5.192ms 1 1 100.00
hmac_test_sha384_vectors 19.860s 1.119ms 1 1 100.00
hmac_test_sha512_vectors 5.564m 20.820ms 1 1 100.00
hmac_test_hmac256_vectors 9.940s 682.268us 1 1 100.00
hmac_test_hmac384_vectors 7.450s 464.317us 1 1 100.00
hmac_test_hmac512_vectors 8.490s 243.184us 1 1 100.00
V2 burst_wr hmac_burst_wr 2.160s 76.313us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 10.685m 4.947ms 1 1 100.00
V2 error hmac_error 1.244m 22.490ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.169m 87.562ms 1 1 100.00
V2 save_and_restore hmac_smoke 1.640s 17.579us 1 1 100.00
hmac_long_msg 1.038m 10.904ms 1 1 100.00
hmac_back_pressure 1.007m 6.173ms 1 1 100.00
hmac_datapath_stress 10.685m 4.947ms 1 1 100.00
hmac_burst_wr 2.160s 76.313us 1 1 100.00
hmac_stress_all 2.048m 6.198ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 1.640s 17.579us 1 1 100.00
hmac_long_msg 1.038m 10.904ms 1 1 100.00
hmac_back_pressure 1.007m 6.173ms 1 1 100.00
hmac_datapath_stress 10.685m 4.947ms 1 1 100.00
hmac_wipe_secret 1.169m 87.562ms 1 1 100.00
hmac_test_sha256_vectors 3.000m 5.192ms 1 1 100.00
hmac_test_sha384_vectors 19.860s 1.119ms 1 1 100.00
hmac_test_sha512_vectors 5.564m 20.820ms 1 1 100.00
hmac_test_hmac256_vectors 9.940s 682.268us 1 1 100.00
hmac_test_hmac384_vectors 7.450s 464.317us 1 1 100.00
hmac_test_hmac512_vectors 8.490s 243.184us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 1.640s 17.579us 1 1 100.00
hmac_long_msg 1.038m 10.904ms 1 1 100.00
hmac_back_pressure 1.007m 6.173ms 1 1 100.00
hmac_datapath_stress 10.685m 4.947ms 1 1 100.00
hmac_burst_wr 2.160s 76.313us 1 1 100.00
hmac_error 1.244m 22.490ms 1 1 100.00
hmac_wipe_secret 1.169m 87.562ms 1 1 100.00
hmac_test_sha256_vectors 3.000m 5.192ms 1 1 100.00
hmac_test_sha384_vectors 19.860s 1.119ms 1 1 100.00
hmac_test_sha512_vectors 5.564m 20.820ms 1 1 100.00
hmac_test_hmac256_vectors 9.940s 682.268us 1 1 100.00
hmac_test_hmac384_vectors 7.450s 464.317us 1 1 100.00
hmac_test_hmac512_vectors 8.490s 243.184us 1 1 100.00
hmac_stress_all 2.048m 6.198ms 1 1 100.00
V2 stress_all hmac_stress_all 2.048m 6.198ms 1 1 100.00
V2 alert_test hmac_alert_test 1.410s 14.078us 1 1 100.00
V2 intr_test hmac_intr_test 1.390s 38.897us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.530s 247.237us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.530s 247.237us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.590s 21.969us 1 1 100.00
hmac_csr_rw 1.570s 21.076us 1 1 100.00
hmac_csr_aliasing 4.880s 623.282us 1 1 100.00
hmac_same_csr_outstanding 2.270s 302.830us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.590s 21.969us 1 1 100.00
hmac_csr_rw 1.570s 21.076us 1 1 100.00
hmac_csr_aliasing 4.880s 623.282us 1 1 100.00
hmac_same_csr_outstanding 2.270s 302.830us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.740s 188.528us 1 1 100.00
hmac_tl_intg_err 4.160s 232.453us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.160s 232.453us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 1.640s 17.579us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.350s 284.052us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.208m 6.408ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.830s 17.761us 1 1 100.00
TOTAL 28 28 100.00