I2C Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	43.360s	1.484ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.560s	1.786ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.720s	41.490us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.490s	36.392us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.550s	475.384us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.110s	232.778us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.840s	160.154us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.490s	36.392us	1	1	100.00
		i2c_csr_aliasing	2.110s	232.778us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.330s	428.881us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	18.718m	24.574ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	17.390s	556.477us	1	1	100.00
V2	host_override	i2c_host_override	1.480s	18.232us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.540m	2.586ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	45.760s	9.536ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.060s	171.178us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.430s	1.112ms	1	1	100.00
		i2c_host_fifo_reset_rx	8.860s	214.637us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	44.200s	17.905ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.270s	1.583ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.980s	62.820us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.790s	2.409ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	16.890m	58.282ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.830s	942.834us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	8.060s	2.940ms	1	1	100.00
		i2c_target_intr_smoke	5.650s	1.949ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.970s	733.862us	1	1	100.00
		i2c_target_fifo_reset_tx	1.580s	232.820us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.147m	27.122ms	1	1	100.00
		i2c_target_stress_rd	8.060s	2.940ms	1	1	100.00
		i2c_target_intr_stress_wr	53.640s	30.272ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.150s	1.401ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.620s	3.760ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.720s	2.046ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.520s	319.628us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.610s	3.938ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.050s	99.233us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	17.390s	556.477us	1	1	100.00
		i2c_host_perf_precise	2.720s	251.015us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.270s	1.583ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.350s	149.769us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.870s	1.930ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.750s	1.932ms	1	1	100.00
		i2c_target_nack_txstretch	1.970s	1.448ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.920s	1.468ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.430s	482.472us	1	1	100.00
V2	alert_test	i2c_alert_test	1.450s	16.043us	1	1	100.00
V2	intr_test	i2c_intr_test	1.530s	17.585us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.330s	83.128us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.330s	83.128us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.720s	41.490us	1	1	100.00
		i2c_csr_rw	1.490s	36.392us	1	1	100.00
		i2c_csr_aliasing	2.110s	232.778us	1	1	100.00
		i2c_same_csr_outstanding	1.950s	101.100us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.720s	41.490us	1	1	100.00
		i2c_csr_rw	1.490s	36.392us	1	1	100.00
		i2c_csr_aliasing	2.110s	232.778us	1	1	100.00
		i2c_same_csr_outstanding	1.950s	101.100us	1	1	100.00
V2		TOTAL			38	38	100.00
V2S	tl_intg_err	i2c_tl_intg_err	2.770s	158.325us	1	1	100.00
		i2c_sec_cm	1.790s	305.554us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.770s	158.325us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	13.800s	2.825ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.000s	233.041us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	14.960s	1.968ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			47	50	94.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.53354533962532488898005773865856318337398231311180931490728855551180865035724
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 233040583 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (0 [0x0] vs 255 [0xff])
        UVM_INFO @ 233040583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.1967402360731073695183495526062618214890934562269815120913151646003382426286
      Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2824913746 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2824913746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.25230381281652475640572586285887051842668984381299613394818828406643456399406
      Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1967584867 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1967584867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---