KEYMGR Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: `c0fece9`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.670s	63.162us	1	1	100.00
V1	random	keymgr_random	33.060s	1.448ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.780s	51.549us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.710s	18.539us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.350s	520.165us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.780s	974.355us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.350s	154.501us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.710s	18.539us	1	1	100.00
		keymgr_csr_aliasing	4.780s	974.355us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.080s	65.715us	1	1	100.00
V2	sideload	keymgr_sideload	4.210s	507.481us	1	1	100.00
		keymgr_sideload_kmac	3.220s	46.279us	1	1	100.00
		keymgr_sideload_aes	2.820s	142.253us	1	1	100.00
		keymgr_sideload_otbn	29.920s	2.712ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.850s	187.949us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.010s	75.498us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.130s	124.847us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.270s	997.745us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.890s	65.804us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.160s	44.433us	1	1	100.00
V2	stress_all	keymgr_stress_all	3.560s	85.244us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.710s	16.479us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.770s	85.944us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.570s	39.824us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.570s	39.824us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.780s	51.549us	1	1	100.00
		keymgr_csr_rw	1.710s	18.539us	1	1	100.00
		keymgr_csr_aliasing	4.780s	974.355us	1	1	100.00
		keymgr_same_csr_outstanding	1.680s	13.865us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.780s	51.549us	1	1	100.00
		keymgr_csr_rw	1.710s	18.539us	1	1	100.00
		keymgr_csr_aliasing	4.780s	974.355us	1	1	100.00
		keymgr_same_csr_outstanding	1.680s	13.865us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
		keymgr_tl_intg_err	1.670s	12.446us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.540s	255.235us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.540s	255.235us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.540s	255.235us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.540s	255.235us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	8.160s	892.560us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.670s	12.446us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.540s	255.235us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.080s	65.715us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	33.060s	1.448ms	1	1	100.00
		keymgr_csr_rw	1.710s	18.539us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	33.060s	1.448ms	1	1	100.00
		keymgr_csr_rw	1.710s	18.539us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	33.060s	1.448ms	1	1	100.00
		keymgr_csr_rw	1.710s	18.539us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.010s	75.498us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.890s	65.804us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.890s	65.804us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	33.060s	1.448ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.190s	54.861us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.220s	253.092us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.010s	75.498us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.220s	253.092us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.220s	253.092us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.220s	253.092us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.350s	8.801ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.220s	253.092us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	9.850s	605.446us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_tl_intg_err has 1 failures.

0.keymgr_tl_intg_err.100880196349529723292454024811399372924619131074762262940028901758722191775168
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @  12445841 ps: (keymgr_csr_assert_fpv.sv:490) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @  12445841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 1 failures.

0.keymgr_same_csr_outstanding.2637425328379960208155234270717688833265040586457086403338259090862747316619
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @  13865276 ps: (keymgr_csr_assert_fpv.sv:442) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @  13865276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.107283899917067875405387944080428276764940981479205433642843460077260953094918
    Line 825, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 605446386 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 605446386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```