| V1 |
smoke |
keymgr_dpe_smoke |
10.960s |
690.425us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
2.050s |
33.275us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.740s |
17.097us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
5.020s |
2.842ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
5.090s |
224.880us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
2.350s |
110.579us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.740s |
17.097us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.090s |
224.880us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.630s |
27.276us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.810s |
28.928us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.840s |
44.305us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.840s |
44.305us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
2.050s |
33.275us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.740s |
17.097us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.090s |
224.880us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
3.480s |
282.592us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
2.050s |
33.275us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.740s |
17.097us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.090s |
224.880us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
3.480s |
282.592us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
7.910s |
489.769us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.950s |
126.055us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
3.060s |
102.416us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
3.060s |
102.416us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
3.060s |
102.416us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
3.060s |
102.416us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
4.080s |
235.347us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
7.910s |
489.769us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
7.910s |
489.769us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |