KMAC/MASKED Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.380s	371.787us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.010s	44.070us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.890s	23.203us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.080s	297.642us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.010s	390.763us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.640s	228.237us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.890s	23.203us	1	1	100.00
		kmac_csr_aliasing	7.010s	390.763us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.700s	115.477us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.980s	75.588us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	14.789m	45.588ms	1	1	100.00
V2	burst_write	kmac_burst_write	14.713m	29.980ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.280s	11.427ms	1	1	100.00
		kmac_test_vectors_sha3_256	35.760s	10.611ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.960s	2.402ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.959m	36.070ms	1	1	100.00
		kmac_test_vectors_shake_128	35.651m	246.242ms	1	1	100.00
		kmac_test_vectors_shake_256	1.687m	5.379ms	1	1	100.00
		kmac_test_vectors_kmac	3.150s	91.078us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.850s	82.041us	1	1	100.00
V2	sideload	kmac_sideload	14.570s	2.222ms	1	1	100.00
V2	app	kmac_app	2.540m	17.259ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.287m	3.692ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.123m	14.084ms	1	1	100.00
V2	error	kmac_error	4.388m	10.205ms	1	1	100.00
V2	key_error	kmac_key_error	2.200s	272.187us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.320s	207.248us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.230s	2.608ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.360s	2.253ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	56.280s	77.711ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.200s	49.255us	1	1	100.00
V2	stress_all	kmac_stress_all	24.959m	106.797ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.750s	41.093us	1	1	100.00
V2	alert_test	kmac_alert_test	2.030s	33.293us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.160s	379.585us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.160s	379.585us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.010s	44.070us	1	1	100.00
		kmac_csr_rw	1.890s	23.203us	1	1	100.00
		kmac_csr_aliasing	7.010s	390.763us	1	1	100.00
		kmac_same_csr_outstanding	2.240s	78.715us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.010s	44.070us	1	1	100.00
		kmac_csr_rw	1.890s	23.203us	1	1	100.00
		kmac_csr_aliasing	7.010s	390.763us	1	1	100.00
		kmac_same_csr_outstanding	2.240s	78.715us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.070s	52.654us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.070s	52.654us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.070s	52.654us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.070s	52.654us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.360s	1.245ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.302m	13.681ms	1	1	100.00
		kmac_tl_intg_err	1.660s	8.829us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.660s	8.829us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.200s	49.255us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.380s	371.787us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	14.570s	2.222ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.070s	52.654us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.302m	13.681ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.302m	13.681ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.302m	13.681ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.380s	371.787us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.200s	49.255us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.302m	13.681ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	42.070s	4.004ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.380s	371.787us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.960s	19.604ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.51151169873824612867533904857127676172648995026993948625264239338490347892760
      Line 152, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19604050090 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 19604050090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.84676558223638468977160678975573168763453123409162212739039624976847619848688
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @   8829156 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @   8829156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---