KMAC/UNMASKED Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	11.590s	2.643ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	33.683us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.540s	20.936us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.510s	1.169ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.720s	413.217us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.300s	34.686us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.540s	20.936us	1	1	100.00
		kmac_csr_aliasing	7.720s	413.217us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.680s	13.376us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.050s	70.622us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	22.104m	145.839ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.150s	3.716ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.640s	628.450us	1	1	100.00
		kmac_test_vectors_sha3_256	28.686m	949.060ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.490s	3.317ms	1	1	100.00
		kmac_test_vectors_sha3_512	8.731m	98.118ms	1	1	100.00
		kmac_test_vectors_shake_128	29.787m	318.762ms	1	1	100.00
		kmac_test_vectors_shake_256	23.997m	248.664ms	1	1	100.00
		kmac_test_vectors_kmac	2.770s	91.384us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.050s	86.625us	1	1	100.00
V2	sideload	kmac_sideload	4.137m	17.984ms	1	1	100.00
V2	app	kmac_app	3.130m	13.995ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.237m	93.561ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	55.020s	3.492ms	1	1	100.00
V2	error	kmac_error	3.565m	55.536ms	1	1	100.00
V2	key_error	kmac_key_error	2.060s	432.058us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.270s	133.530us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	24.960s	2.723ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	20.460s	640.639us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	7.710s	11.660ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.890s	50.803us	1	1	100.00
V2	stress_all	kmac_stress_all	9.078m	89.680ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.720s	31.831us	1	1	100.00
V2	alert_test	kmac_alert_test	2.030s	22.531us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.700s	143.061us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.700s	143.061us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	33.683us	1	1	100.00
		kmac_csr_rw	1.540s	20.936us	1	1	100.00
		kmac_csr_aliasing	7.720s	413.217us	1	1	100.00
		kmac_same_csr_outstanding	2.420s	135.140us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	33.683us	1	1	100.00
		kmac_csr_rw	1.540s	20.936us	1	1	100.00
		kmac_csr_aliasing	7.720s	413.217us	1	1	100.00
		kmac_same_csr_outstanding	2.420s	135.140us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.160s	217.018us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.160s	217.018us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.160s	217.018us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.160s	217.018us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.600s	156.294us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	39.330s	3.467ms	1	1	100.00
		kmac_tl_intg_err	3.190s	132.926us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.190s	132.926us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.890s	50.803us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	11.590s	2.643ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.137m	17.984ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.160s	217.018us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	39.330s	3.467ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	39.330s	3.467ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	39.330s	3.467ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	11.590s	2.643ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.890s	50.803us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	39.330s	3.467ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.083m	17.002ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	11.590s	2.643ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.030s	2.697ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.98425768308017949713737652773355843964164723063172010675039089641320544302701
      Line 159, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2696965283 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2696965283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---