c0fece9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.667m | 7.613ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 3.000s | 12.696us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 13.264us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 119.261us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 14.304us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 988.755ns | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 13.264us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 14.304us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 1.567m | 29.389ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.167m | 1.256ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 1.000m | 4.648ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 5.000s | 14.345us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 14.127us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 14.127us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 3.000s | 12.696us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 13.264us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 14.304us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 15.327us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 3.000s | 12.696us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 13.264us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 14.304us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 15.327us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 9.000s | 22.533us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 6.301us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.44843564313298653723318920571384470644694035175904844173070865064089097563015
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 14126668 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x9eaf821f a_data = 0x99b0a16c a_mask = 0x3 a_size = 0x3 a_param = 0x0 a_source = 0xce a_opcode = Get a_user = 0x25d1f d_data = 0xd770fad9 d_size = 0x2 d_param = 0x0 d_source = 0x30 d_opcode = AccessAck d_error = 0 d_user = 1111111001010 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 14126668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.31602284465996220927554401828764963977442729463732009104622618140267492944454
Line 102, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 6300810 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x138b6d65 a_data = 0x65b30b37 a_mask = 0x3 a_size = 0x0 a_param = 0x0 a_source = 0x8f a_opcode = Get a_user = 0x5695 d_data = 0x5d67abba d_size = 0x3 d_param = 0x0 d_source = 0xf2 d_opcode = AccessAckData d_error = 0 d_user = 1001001011010 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 6300810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.33727486409051379696605934787042302963036791203871139183441929441731639797615
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 988755 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x2cd68a20 a_data = 0x14e4f5af a_mask = 0x0 a_size = 0x0 a_param = 0x0 a_source = 0x51 a_opcode = Invalid, value: 3 a_user = 0x24768 d_data = 0xcfa000bf d_size = 0x3 d_param = 0x0 d_source = 0x66 d_opcode = AccessAck d_error = 0 d_user = 1101100101 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 988755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---