OTBN Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: `c0fece9`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	50.814us	1	1	100.00
V1	single_binary	otbn_single	11.000s	220.191us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	25.342us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	44.544us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	76.755us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	46.348us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	28.506us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	44.544us	1	1	100.00
		otbn_csr_aliasing	7.000s	46.348us	1	1	100.00
V1	mem_walk	otbn_mem_walk	17.000s	928.080us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	1.470ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	1.267m	381.165us	1	1	100.00
V2	multi_error	otbn_multi_err	55.000s	1.933ms	1	1	100.00
V2	back_to_back	otbn_multi	50.000s	757.935us	1	1	100.00
V2	stress_all	otbn_stress_all	1.017m	196.486us	1	1	100.00
V2	lc_escalation	otbn_escalate	7.000s	1.996us	0	1	0.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	14.221us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	24.206us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	56.844us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	34.982us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	91.289us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	91.289us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	25.342us	1	1	100.00
		otbn_csr_rw	6.000s	44.544us	1	1	100.00
		otbn_csr_aliasing	7.000s	46.348us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	149.400us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	25.342us	1	1	100.00
		otbn_csr_rw	6.000s	44.544us	1	1	100.00
		otbn_csr_aliasing	7.000s	46.348us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	149.400us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	9.000s	36.392us	1	1	100.00
		otbn_dmem_err	12.000s	36.998us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	206.344us	1	1	100.00
		otbn_controller_ispr_rdata_err	12.000s	25.257us	1	1	100.00
		otbn_mac_bignum_acc_err	12.000s	59.866us	1	1	100.00
		otbn_urnd_err	6.000s	16.435us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	16.541us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	12.293us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	48.911us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	9.000s	36.286us	0	1	0.00
		otbn_tl_intg_err	11.000s	215.134us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	6.000s	2.037us	0	1	0.00
V2S	prim_fsm_check	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	50.814us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	36.998us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	36.392us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	11.000s	215.134us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	7.000s	1.996us	0	1	0.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	36.392us	1	1	100.00
		otbn_dmem_err	12.000s	36.998us	1	1	100.00
		otbn_zero_state_err_urnd	11.000s	14.221us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	16.541us	1	1	100.00
		otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	36.392us	1	1	100.00
		otbn_dmem_err	12.000s	36.998us	1	1	100.00
		otbn_zero_state_err_urnd	11.000s	14.221us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	16.541us	1	1	100.00
		otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	7.000s	1.996us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	36.392us	1	1	100.00
		otbn_dmem_err	12.000s	36.998us	1	1	100.00
		otbn_zero_state_err_urnd	11.000s	14.221us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	16.541us	1	1	100.00
		otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	113.844us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	25.183us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	20.000s	321.294us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	20.000s	321.294us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	36.117us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	255.441us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	76.049us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	76.049us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	19.166us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	50.000s	757.935us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	49.046us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	11.000s	220.191us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.000s	36.286us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.950m	5.402ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	41	90.24

Failure Buckets

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 0.otbn_escalate.84985109067667326433735182068009847067477881765371363659568916670518999574952
    Line 101, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
```
  UVM_ERROR @   1995958 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   1995958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.89727657882303642974805546658395530127074152222148448788212728906841689552544
    Line 215, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5401739073 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5401739073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 0.otbn_passthru_mem_tl_intg_err.115636673334631454514131063022071312585594991727279874734493532289944342865422
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   2037069 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   2037069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.35828259474987773014916553697149449282328976252631684663276488870281758050439
Line 88, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 36285577 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 36285577 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  36285577 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  36285577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---