ROM_CTRL/32KB Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.620s 549.136us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.870s 396.356us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.800s 453.989us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.670s 1.171ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.540s 658.078us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.360s 312.302us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.800s 453.989us 1 1 100.00
rom_ctrl_csr_aliasing 4.540s 658.078us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.390s 297.524us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.750s 213.979us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.310s 608.541us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.950s 467.562us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.450s 307.328us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.000s 385.277us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.850s 164.433us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.850s 164.433us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.870s 396.356us 1 1 100.00
rom_ctrl_csr_rw 3.800s 453.989us 1 1 100.00
rom_ctrl_csr_aliasing 4.540s 658.078us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 206.240us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.870s 396.356us 1 1 100.00
rom_ctrl_csr_rw 3.800s 453.989us 1 1 100.00
rom_ctrl_csr_aliasing 4.540s 658.078us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 206.240us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 18.600s 581.131us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.864m 2.052ms 1 1 100.00
rom_ctrl_tl_intg_err 39.800s 779.860us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.864m 2.052ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.864m 2.052ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.864m 2.052ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.864m 2.052ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.620s 549.136us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.620s 549.136us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.620s 549.136us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 39.800s 779.860us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.450s 307.328us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 44.140s 5.146ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 18.600s 581.131us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.864m 2.052ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.717m 8.784ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00