ROM_CTRL/64KB Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.700s 304.005us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.990s 1.061ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.370s 290.801us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.420s 298.968us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.930s 1.010ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.670s 316.042us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.370s 290.801us 1 1 100.00
rom_ctrl_csr_aliasing 6.930s 1.010ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.650s 214.883us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.860s 1.071ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.510s 225.029us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.050s 2.959ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.090s 580.185us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.940s 1.071ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.900s 383.535us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.900s 383.535us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.990s 1.061ms 1 1 100.00
rom_ctrl_csr_rw 7.370s 290.801us 1 1 100.00
rom_ctrl_csr_aliasing 6.930s 1.010ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.680s 1.032ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.990s 1.061ms 1 1 100.00
rom_ctrl_csr_rw 7.370s 290.801us 1 1 100.00
rom_ctrl_csr_aliasing 6.930s 1.010ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.680s 1.032ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 29.730s 4.331ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.476m 444.684us 1 1 100.00
rom_ctrl_tl_intg_err 1.033m 1.728ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.476m 444.684us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.476m 444.684us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.476m 444.684us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.476m 444.684us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.700s 304.005us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.700s 304.005us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.700s 304.005us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.033m 1.728ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.090s 580.185us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.559m 2.913ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 29.730s 4.331ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.476m 444.684us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 32.420s 5.209ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00