| V1 |
random |
rv_timer_random |
1.520s |
100.116us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.500s |
64.484us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.410s |
31.344us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
3.140s |
131.611us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.430s |
13.908us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.620s |
53.200us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.410s |
31.344us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.430s |
13.908us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.510s |
14.884us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
3.050s |
909.501us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
2.613m |
141.469ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
2.613m |
141.469ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
4.850s |
9.742ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.500s |
40.352us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.490s |
13.266us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.790s |
247.969us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.790s |
247.969us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.500s |
64.484us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.410s |
31.344us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.430s |
13.908us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.630s |
122.115us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.500s |
64.484us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.410s |
31.344us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.430s |
13.908us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.630s |
122.115us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.860s |
143.130us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.770s |
214.979us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.770s |
214.979us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.470s |
16.408us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.570s |
19.414us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
7.140s |
752.903us |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |