SPI_DEVICE/1R1W Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.160m	13.444ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.180s	44.707us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.670s	230.448us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.440s	713.731us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.320s	3.094ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.290s	24.695us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.670s	230.448us	1	1	100.00
		spi_device_csr_aliasing	11.320s	3.094ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.600s	10.763us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.890s	69.734us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.660s	29.266us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.600s	6.319us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.650s	3.805us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.860s	91.769us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.860s	91.769us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.500s	1.153ms	1	1	100.00
		spi_device_tpm_sts_read	1.610s	22.151us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.900s	1.925ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	17.240s	23.097ms	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.500s	2.488ms	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.500s	2.488ms	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.840s	867.746us	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.840s	867.746us	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.840s	867.746us	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.840s	867.746us	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.840s	867.746us	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.570s	1.730ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.810s	1.084ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.810s	1.084ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.810s	1.084ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	20.270s	1.528ms	1	1	100.00
		spi_device_read_buffer_direct	7.960s	20.160ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.810s	1.084ms	1	1	100.00
		spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	10.240s	4.306ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.450s	88.649us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.450s	88.649us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.160m	13.444ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	47.120s	8.552ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.110s	302.272us	1	1	100.00
V2	alert_test	spi_device_alert_test	2.020s	11.370us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.670s	45.953us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.720s	411.544us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.720s	411.544us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.180s	44.707us	1	1	100.00
		spi_device_csr_rw	2.670s	230.448us	1	1	100.00
		spi_device_csr_aliasing	11.320s	3.094ms	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	91.084us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.180s	44.707us	1	1	100.00
		spi_device_csr_rw	2.670s	230.448us	1	1	100.00
		spi_device_csr_aliasing	11.320s	3.094ms	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	91.084us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.210s	38.035us	1	1	100.00
		spi_device_tl_intg_err	16.640s	876.658us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.640s	876.658us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.860s	258.647us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.26987082327316314322659664919458435021504928617810524638328865536847971229167
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   5038692 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[49])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   5038692 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   5038692 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[945])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.31905137449673898860607989530928732738376575741921688372533287407821190148459
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1497028 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x422654 [10000100010011001010100] vs 0x0 [0])
        UVM_ERROR @   1523028 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8d2f64 [100011010010111101100100] vs 0x0 [0])
        UVM_ERROR @   1577028 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ab0b9 [1010101011000010111001] vs 0x0 [0])
        UVM_ERROR @   1633028 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x14c77f [101001100011101111111] vs 0x0 [0])
        UVM_ERROR @   1660028 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfbf920 [111110111111100100100000] vs 0x0 [0])