SPI_HOST Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	45.000s	4.925ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	41.771us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	16.855us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	204.889us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	33.795us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	78.395us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	16.855us	1	1	100.00
		spi_host_csr_aliasing	3.000s	33.795us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	44.544us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	95.585us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	59.674us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	174.283us	1	1	100.00
		spi_host_error_cmd	4.000s	58.743us	1	1	100.00
		spi_host_event	1.533m	3.161ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	164.882us	1	1	100.00
V2	speed	spi_host_speed	4.000s	164.882us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	164.882us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	1.000m	2.365ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	91.742us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	164.882us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	164.882us	1	1	100.00
V2	duplex	spi_host_smoke	45.000s	4.925ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	45.000s	4.925ms	1	1	100.00
V2	stress_all	spi_host_stress_all	12.000s	586.372us	1	1	100.00
V2	spien	spi_host_spien	5.000s	341.123us	1	1	100.00
V2	stall	spi_host_status_stall	23.000s	1.936ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	197.181us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	174.283us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	28.495us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	40.718us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	90.133us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	90.133us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	41.771us	1	1	100.00
		spi_host_csr_rw	4.000s	16.855us	1	1	100.00
		spi_host_csr_aliasing	3.000s	33.795us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	65.549us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	41.771us	1	1	100.00
		spi_host_csr_rw	4.000s	16.855us	1	1	100.00
		spi_host_csr_aliasing	3.000s	33.795us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	65.549us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	488.787us	1	1	100.00
		spi_host_sec_cm	3.000s	180.826us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	488.787us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.500m	36.700ms	1	1	100.00
		TOTAL			26	26	100.00