SRAM_CTRL/MAIN Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.190s	1.026ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.720s	20.813us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.660s	22.293us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.300s	180.492us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.580s	14.664us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.140s	706.680us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.660s	22.293us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	14.664us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.993m	57.529ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.121m	11.850ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.855m	6.500ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.083m	12.512ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.378m	110.437ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.947m	59.145ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	38.360s	22.480ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.473m	21.965ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	50.670s	908.342us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.948m	5.992ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	16.660s	13.791ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.120s	1.395ms	1	1	100.00
		sram_ctrl_throughput_w_readback	13.790s	3.705ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.465m	71.947ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.120s	724.021us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	46.431m	288.668ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.440s	45.797us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.220s	23.629us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.220s	23.629us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.720s	20.813us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	22.293us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	14.664us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	33.673us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.720s	20.813us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	22.293us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	14.664us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	33.673us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.750s	54.215ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.510s	2.278us	0	1	0.00
		sram_ctrl_tl_intg_err	3.310s	663.680us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.510s	2.278us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.310s	663.680us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.465m	71.947ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.465m	71.947ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.660s	22.293us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.473m	21.965ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.473m	21.965ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.473m	21.965ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	38.360s	22.480ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.560s	747.728us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.750s	54.215ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.890s	1.844ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.190s	1.026ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.190s	1.026ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.473m	21.965ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.510s	2.278us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	38.360s	22.480ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.510s	2.278us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.510s	2.278us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.190s	1.026ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.510s	2.278us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	19.890s	7.188ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.70734278525253722197292508361468444700187897135868253357050168054227317403344
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2277840 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2277840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---