SRAM_CTRL/RET Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 11.510s 655.561us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.650s 22.247us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.600s 15.410us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.160s 241.710us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.690s 66.900us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.690s 69.900us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.600s 15.410us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 66.900us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 5.090s 376.417us 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.580s 318.949us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 5.727m 9.507ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 2.940m 5.190ms 1 1 100.00
V2 bijection sram_ctrl_bijection 55.630s 17.327ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 6.279m 43.827ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 6.270s 1.358ms 1 1 100.00
V2 executable sram_ctrl_executable 5.926m 3.638ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 7.200s 1.683ms 1 1 100.00
sram_ctrl_partial_access_b2b 5.518m 76.045ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 32.290s 108.481us 1 1 100.00
sram_ctrl_throughput_w_partial_write 22.920s 121.097us 1 1 100.00
sram_ctrl_throughput_w_readback 20.600s 196.839us 1 1 100.00
V2 regwen sram_ctrl_regwen 6.551m 9.492ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.800s 82.297us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 37.859m 90.744ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.610s 37.078us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.570s 45.428us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.570s 45.428us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.650s 22.247us 1 1 100.00
sram_ctrl_csr_rw 1.600s 15.410us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 66.900us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.550s 22.740us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.650s 22.247us 1 1 100.00
sram_ctrl_csr_rw 1.600s 15.410us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 66.900us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.550s 22.740us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 2.380s 442.072us 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.960s 12.329us 0 1 0.00
sram_ctrl_tl_intg_err 2.900s 442.110us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.960s 12.329us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.900s 442.110us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 6.551m 9.492ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 6.551m 9.492ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.600s 15.410us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 5.926m 3.638ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 5.926m 3.638ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 5.926m 3.638ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 6.270s 1.358ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 1.820s 149.489us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 2.380s 442.072us 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 1.960s 85.301us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 11.510s 655.561us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 11.510s 655.561us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 5.926m 3.638ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.960s 12.329us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 6.270s 1.358ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.960s 12.329us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.960s 12.329us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 11.510s 655.561us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.960s 12.329us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 2.080m 1.659ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets