UART Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.610s	653.300us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	48.670us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.560s	17.027us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.650s	58.809us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.490s	65.852us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.020s	156.984us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.560s	17.027us	1	1	100.00
		uart_csr_aliasing	1.490s	65.852us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	12.110s	94.872ms	1	1	100.00
V2	parity	uart_smoke	2.610s	653.300us	1	1	100.00
		uart_tx_rx	12.110s	94.872ms	1	1	100.00
V2	parity_error	uart_intr	9.230s	3.223ms	1	1	100.00
		uart_rx_parity_err	14.070s	19.327ms	1	1	100.00
V2	watermark	uart_tx_rx	12.110s	94.872ms	1	1	100.00
		uart_intr	9.230s	3.223ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.377m	154.449ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.100m	290.070ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	38.110s	249.128ms	1	1	100.00
V2	rx_frame_err	uart_intr	9.230s	3.223ms	1	1	100.00
V2	rx_break_err	uart_intr	9.230s	3.223ms	1	1	100.00
V2	rx_timeout	uart_intr	9.230s	3.223ms	1	1	100.00
V2	perf	uart_perf	1.532m	12.840ms	1	1	100.00
V2	sys_loopback	uart_loopback	8.540s	4.313ms	1	1	100.00
V2	line_loopback	uart_loopback	8.540s	4.313ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	12.910s	6.271ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.390s	2.920ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	15.420s	6.717ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	10.470s	3.160ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.016m	71.327ms	1	1	100.00
V2	stress_all	uart_stress_all	3.099m	182.711ms	1	1	100.00
V2	alert_test	uart_alert_test	1.630s	23.453us	1	1	100.00
V2	intr_test	uart_intr_test	1.570s	12.271us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.810s	40.864us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.810s	40.864us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	48.670us	1	1	100.00
		uart_csr_rw	1.560s	17.027us	1	1	100.00
		uart_csr_aliasing	1.490s	65.852us	1	1	100.00
		uart_same_csr_outstanding	1.530s	26.733us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	48.670us	1	1	100.00
		uart_csr_rw	1.560s	17.027us	1	1	100.00
		uart_csr_aliasing	1.490s	65.852us	1	1	100.00
		uart_same_csr_outstanding	1.530s	26.733us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.730s	555.854us	1	1	100.00
		uart_tl_intg_err	2.000s	359.102us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.000s	359.102us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	15.980s	1.822ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00