CHIP Simulation Results

Monday June 16 2025 17:01:07 UTC

GitHub Revision: `c0fece9`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.312m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.312m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	3.473m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	3.221m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.438m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.135m	4.882ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.135m	4.882ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.135m	4.882ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	28.470s	10.120us	0	1	0.00
		chip_sw_example_manufacturer	30.432s		0	1	0.00
		chip_sw_example_concurrency	5.269m	4.274ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.998s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.410s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.100s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.100s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.570s	12.793us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	4.357m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.259m	8.532ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.423m	5.570ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.750m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.664m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	2.330m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	2.100m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.830s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.830s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.930m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.145m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.884m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.884m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.768m	4.674ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.939m	3.521ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.070m	14.212ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.450s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.362s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	17.553m	26.251ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.732m	6.513ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.614m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.614m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	37.247s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.594m	5.444ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.594m	5.444ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.335m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.392m	4.624ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.474m	6.101ms	1	1	100.00
		chip_sw_aes_idle	4.539m	5.054ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.242m	3.747ms	1	1	100.00
		chip_sw_kmac_idle	3.992m	3.839ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.026m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.187m	12.024ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.160m	11.993ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	12.790m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.592s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.774s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.825s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.515s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.902s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.101s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.151s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.592s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.774s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.825s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.515s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.902s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.101s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.151s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	17.090s		0	1	0.00
		chip_sw_aes_enc_jitter_en	35.260s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.570s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.790s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	34.840s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.664s		0	1	0.00
		chip_sw_clkmgr_jitter	4.189m	5.457ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.491m	3.602ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.962s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	33.660s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	33.940s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	36.340s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.330s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.990s	10.160us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.872s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.454s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.587s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.405s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.661m	13.829ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.725m	13.714ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.594m	5.444ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	15.588s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.725m	13.714ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	20.576s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.721s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	36.424s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	43.646s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	19.299s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.661m	13.829ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.070m	14.212ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	26.472m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.387m	7.499ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.136m	6.001ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.520m	5.534ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.661m	13.829ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.571s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.987s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.661m	13.829ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.153s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.136m	6.001ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.097s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.968s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.800s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.695s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.818s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.923s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.987s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.620s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.662m	9.812ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	32.458s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	40.993s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.125s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.191s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.897m	10.019ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.138m	13.280ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	14.860s		0	1	0.00
		chip_prim_tl_access	7.621m	17.796ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.592s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.774s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.825s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.515s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.902s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.101s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.151s		0	1	0.00
		chip_rv_dm_lc_disabled	17.553m	26.251ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.175m	5.711ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	35.260s	10.240us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.316m	5.585ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.539m	5.054ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.574m	4.574ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	35.570s	10.280us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.242m	3.747ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.386m	4.100ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.407m	3.374ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	34.840s	10.300us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.897m	10.019ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	29.360s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.036m	5.426ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.992m	3.839ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.897s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.897s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.386s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.819m	4.464ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.331s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.897m	10.019ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.790s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.866s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	17.090s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.474m	6.101ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.474m	6.101ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.474m	6.101ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.398m	5.794ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.138m	13.280ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.138m	13.280ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.577m	6.865ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.664s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.860s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.661m	13.829ms	1	1	100.00
		chip_sw_data_integrity_escalation	4.884m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.398m	5.794ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.897m	10.019ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.577m	6.865ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.851m	3.880ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.398m	5.794ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.897m	10.019ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.577m	6.865ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.851m	3.880ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.740s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.620s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	32.458s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	40.993s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.125s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.191s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.313s		0	1	0.00
		chip_prim_tl_access	7.621m	17.796ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.621m	17.796ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	29.914s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.077s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.454s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	17.090s		0	1	0.00
		chip_sw_aes_enc_jitter_en	35.260s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.570s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.790s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	34.840s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.664s		0	1	0.00
		chip_sw_clkmgr_jitter	4.189m	5.457ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.962m	8.081ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.962m	8.081ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.645m	3.838ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.324m	4.742ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.759m	5.718ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.176m	4.466ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.815m	4.540ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.914m	5.416ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.851m	3.880ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	26.472m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	26.472m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.826m	4.538ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.841m	5.591ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.409m	5.921ms	1	1	100.00
		chip_sw_csrng_smoketest	2.941m	3.762ms	1	1	100.00
		chip_sw_gpio_smoketest	4.200m	5.580ms	1	1	100.00
		chip_sw_hmac_smoketest	4.691m	5.775ms	1	1	100.00
		chip_sw_kmac_smoketest	3.734m	4.087ms	1	1	100.00
		chip_sw_otbn_smoketest	4.526m	4.492ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.480m	3.974ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.261m	5.544ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.646m	4.432ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.103m	4.158ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.042m	3.226ms	1	1	100.00
		chip_sw_uart_smoketest	3.561m	3.726ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	15.176s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.998s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.357m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.826s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.552m	5.851ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.582m	4.403ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.642m	5.431ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.852m	5.808ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	36.668s		0	1	0.00
		chip_rv_dm_lc_disabled	17.553m	26.251ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.211s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.174s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.228s		0	1	0.00
		chip_sw_lc_walkthrough_rma	17.730s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	36.668s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	18.066s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	29.486s		0	1	0.00
		rom_volatile_raw_unlock	12.567s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.369s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.717m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	4.229m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.911m	3.368ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.911m	3.368ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.100s		0	1	0.00
		chip_same_csr_outstanding	8.670s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.100s		0	1	0.00
		chip_same_csr_outstanding	8.670s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	51.370s	45.167us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.920s	12.174us	1	1	100.00
		xbar_smoke_large_delays	5.078m	2.787ms	1	1	100.00
		xbar_smoke_slow_rsp	4.448m	1.797ms	1	1	100.00
		xbar_random_zero_delays	49.870s	47.502us	1	1	100.00
		xbar_random_large_delays	25.033m	13.475ms	1	1	100.00
		xbar_random_slow_rsp	29.657m	11.356ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.683m	214.627us	1	1	100.00
		xbar_error_and_unmapped_addr	32.300s	64.147us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.534m	264.315us	1	1	100.00
		xbar_error_and_unmapped_addr	32.300s	64.147us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.210m	152.351us	1	1	100.00
		xbar_access_same_device_slow_rsp	47.399m	19.045ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	37.560s	102.302us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	7.724m	439.773us	1	1	100.00
		xbar_stress_all_with_error	13.509m	2.399ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	50.679m	7.454ms	1	1	100.00
		xbar_stress_all_with_reset_error	3.855m	313.927us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.057s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.611s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	14.484s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.590s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.297s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.168s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.809s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.510s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.082s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.107s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.171s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.231s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.572s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.396s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.196s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.931s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.515s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.213s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.851s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.147s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.561s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.188s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.608s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.631s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.747s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.532s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.211s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.660s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.829s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.576s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.208s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.064s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.426s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.095s		0	1	0.00
		rom_e2e_asm_init_dev	13.138s		0	1	0.00
		rom_e2e_asm_init_prod	12.295s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.372s		0	1	0.00
		rom_e2e_asm_init_rma	12.211s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.420s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.397s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.412s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.199s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.316m	4.111ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.448m	4.838ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.397s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.927s		0	1	0.00
		rom_e2e_jtag_debug_rma	13.181s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.727s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.661m	13.829ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.926s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.791m	12.927ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.338s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.044s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.397s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.927s		0	1	0.00
		rom_e2e_jtag_debug_rma	13.181s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.708s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.997s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.971s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.348m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.300m	13.686ms	1	1	100.00
		chip_plic_all_irqs_0	8.792m	6.787ms	1	1	100.00
		chip_plic_all_irqs_10	10.335m	6.863ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.354m	4.880ms	1	1	100.00
		chip_sw_dma_abort	4.412m	4.952ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.696s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.381s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.961s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.603s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.526s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.148s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.712s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.253s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.044s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.037s		0	1	0.00
		chip_sw_mbx_smoketest	4.930m	6.146ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.60266064025332397228025329041006099197091955162109584958451712970191750831988
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f2707e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 14.400s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.23136729843833454555269839205402492410707230028718490902435511133334849001979
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (d0652d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 282.883s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.69122078842792843214632679064901520025780670495932129126798476620624276750389
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (00b21a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 285.379s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.69002865455195353199963676268738345904308679640064261532879257675540664244136
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (65acf2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 297.318s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.67889808943132306497964047868634479198387240449306574046358047904777362298987
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (bb5f29)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 247.302s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.40997151105219388000582725929841523670968379074254409295571440927785680423195
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.62199544492504601307699322096647657594767263197127695783828776324462443280619
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.31437835013124346118585403716089220704365657979844432582160244715039629815775
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.23612053999687736573620962427776521631474431342003688272867671540488784538890
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.5849954060560996535283551855118006856816610506811981026116501740724826356476
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.35173667598130615385165808113547436832559134817238457372256866755009567428386
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.88087494526647297010078168972020072662714491340933980154168530045157875736737
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.92883766808664822113528889137703411129273183114859031791616939790903672600140
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.36124578925825876934868331211562367828221915783671537107337695674606284440762
Line 480, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.084412 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.084412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.30353856385553872431403394514673654262835176446041833140275192894926406442356
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.491876 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.491876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.29540264178634226144028608724824709694313089143834006448843150401614402844068
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.991521 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.991521 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.12538146059100374959164050960798683467154217981918470896343155884799308506710
Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12014.905807 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.905807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.83136436849028063076141092067233650308547741811012586724905956481659538919172
Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12023.949259 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12023.949259 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.63190488496502671496556977099153110683656470151233051022734074405936911945369
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.845918 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.845918 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.115706842933660571616421099161738595389174584424657891214762652665152966218766
Line 491, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10019.123442 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (11266336972820145093464625508620436203110601171541290110804840927245651589640 [0x18e8854ff3f8d8ef34fad79b7f40a09e818f71fc3382d5a205309658a7d2ba08] vs 61844404020115971834522053251676981565531130514755648615375545055914049576422 [0x88bab135c5269e5e8b3f1eb858828324b68a0b609e67b45615be683391829de6])
  UVM_INFO @ 10019.123442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.4580649929086728722582262932010148765801441528232959778012749982877004841836
Line 485, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9811.819500 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (16336823661580984148117971089220577181203173130146742555742032029611669318349 [0x241e50841512ea411e401dbda4cbe30cabb5cd520b5a38dea9a433d7608feacd] vs 29367480370817103122102770424183399936702809076638003858692745205932076036435 [0x40ed67a4375d69fcffc15e17f878cecd7d66a1dbc482b08ba1b6483d8377f153])
  UVM_INFO @ 9811.819500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.40528857926141431676404771070106060136972593357704073094795152618315771325327
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4673.755394 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h1d674520  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h0  a_user: 'h26930  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4673.755394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.93141038798023369116479489574761228054944152596364086910967349462278293270436
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3520.959420 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h86063e67  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h0  a_user: 'h26969  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3520.959420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.65265075041833092767817255854029536270146149557920325121535566802338196016986
    Line 886, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.38076327977470104176701173430695527291654491540760692844291072636973734728571
    Line 499, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5570.174068 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5570.174068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.88592634726141418412935247667132304986805325133005992021770475541558608225213
    Line 713, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6000.925792 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6000.925792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.3878134336593164840324714825515481676644540597395649387621837565360825970775
    Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3837.632184 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3837.632184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.55774048059434193811660906581324309231308023643430171186309967962870071004501
    Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4742.243674 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4742.243674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.19401768550264748894612741780179006844272766262772706324611183562906790538673
    Line 470, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5444.214800 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5444.214800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.43323263180633459223652572865037108036069243116364609547940393304858610278856
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4466.272376 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4466.272376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.104223460425055419233013636108158844001262159501474489237184871431290657295282
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@40104) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.61094599283912034679548113692924623525188305669181649419206785452047182085138
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3367.628240 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@40104) { a_addr: 'h2212  a_data: 'hd9fc7e9b  a_mask: 'h0  a_size: 'h1  a_param: 'h0  a_source: 'he2  a_opcode: 'h4  a_user: 'h241b8  d_param: 'h0  d_source: 'he2  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3367.628240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.11454328709341182172525999468375550180321394201167730664103367090634455644229
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14212.184964 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14212.184964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.50847504876880707333202156811437415230972892079994709594444860989818743206510
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.19749001675524480066838088065892658859468154926121525502855722640522174706867
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4952.295086 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4952.295086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```