DMA Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	323.383us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.381ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	9.000s	286.882us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	19.076us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	63.946us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	1.039ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	568.029us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	78.743us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	63.946us	1	1	100.00
		dma_csr_aliasing	9.000s	568.029us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.767m	35.277ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.017m	45.680ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.717m	49.563ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1.567m	8.071ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.017m	45.680ms	1	1	100.00
V2	dma_abort	dma_abort	15.000s	946.227us	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.633m	21.012ms	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	17.243us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	428.679us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	428.679us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	19.076us	1	1	100.00
		dma_csr_rw	4.000s	63.946us	1	1	100.00
		dma_csr_aliasing	9.000s	568.029us	1	1	100.00
		dma_same_csr_outstanding	5.000s	40.367us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	19.076us	1	1	100.00
		dma_csr_rw	4.000s	63.946us	1	1	100.00
		dma_csr_aliasing	9.000s	568.029us	1	1	100.00
		dma_same_csr_outstanding	5.000s	40.367us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	152.153us	1	1	100.00
		dma_generic_stress	1.567m	8.071ms	1	1	100.00
		dma_handshake_stress	2.017m	45.680ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	886.278us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	48.000s	4.474ms	1	1	100.00
		dma_longer_transfer	6.000s	827.944us	1	1	100.00
		TOTAL			21	21	100.00