EDN Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.010s	40.362us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.740s	14.770us	1	1	100.00
V1	csr_rw	edn_csr_rw	2.030s	19.598us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.340s	220.070us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.220s	41.753us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.210s	22.258us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	2.030s	19.598us	1	1	100.00
		edn_csr_aliasing	2.220s	41.753us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.180s	107.726us	1	1	100.00
V2	csrng_commands	edn_genbits	2.180s	107.726us	1	1	100.00
V2	genbits	edn_genbits	2.180s	107.726us	1	1	100.00
V2	interrupts	edn_intr	1.640s	30.379us	1	1	100.00
V2	alerts	edn_alert	1.870s	23.636us	1	1	100.00
V2	errs	edn_err	1.930s	21.292us	1	1	100.00
V2	disable	edn_disable	1.760s	17.239us	1	1	100.00
		edn_disable_auto_req_mode	1.860s	31.510us	1	1	100.00
V2	stress_all	edn_stress_all	2.530s	204.861us	1	1	100.00
V2	intr_test	edn_intr_test	1.840s	37.201us	1	1	100.00
V2	alert_test	edn_alert_test	1.890s	44.362us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.190s	128.082us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.190s	128.082us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.740s	14.770us	1	1	100.00
		edn_csr_rw	2.030s	19.598us	1	1	100.00
		edn_csr_aliasing	2.220s	41.753us	1	1	100.00
		edn_same_csr_outstanding	1.800s	24.205us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.740s	14.770us	1	1	100.00
		edn_csr_rw	2.030s	19.598us	1	1	100.00
		edn_csr_aliasing	2.220s	41.753us	1	1	100.00
		edn_same_csr_outstanding	1.800s	24.205us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.090s	892.520us	1	1	100.00
		edn_tl_intg_err	2.930s	99.404us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.150s	30.590us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.870s	23.636us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.090s	892.520us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.090s	892.520us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.090s	892.520us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.090s	892.520us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.870s	23.636us	1	1	100.00
		edn_sec_cm	4.090s	892.520us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.870s	23.636us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.930s	99.404us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	27.970s	6.302ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00