HMAC Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.760s 487.999us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.540s 16.709us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.500s 35.578us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.570s 905.333us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.250s 165.713us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.246m 342.578ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.500s 35.578us 1 1 100.00
hmac_csr_aliasing 3.250s 165.713us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 36.380s 11.865ms 1 1 100.00
V2 back_pressure hmac_back_pressure 27.830s 707.580us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.183m 5.664ms 1 1 100.00
hmac_test_sha384_vectors 6.238m 12.983ms 1 1 100.00
hmac_test_sha512_vectors 19.250s 486.455us 1 1 100.00
hmac_test_hmac256_vectors 9.980s 305.556us 1 1 100.00
hmac_test_hmac384_vectors 7.740s 4.636ms 1 1 100.00
hmac_test_hmac512_vectors 8.680s 875.105us 1 1 100.00
V2 burst_wr hmac_burst_wr 19.120s 500.745us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 11.606m 9.735ms 1 1 100.00
V2 error hmac_error 1.007m 1.659ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.026m 2.062ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.760s 487.999us 1 1 100.00
hmac_long_msg 36.380s 11.865ms 1 1 100.00
hmac_back_pressure 27.830s 707.580us 1 1 100.00
hmac_datapath_stress 11.606m 9.735ms 1 1 100.00
hmac_burst_wr 19.120s 500.745us 1 1 100.00
hmac_stress_all 9.412m 21.324ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.760s 487.999us 1 1 100.00
hmac_long_msg 36.380s 11.865ms 1 1 100.00
hmac_back_pressure 27.830s 707.580us 1 1 100.00
hmac_datapath_stress 11.606m 9.735ms 1 1 100.00
hmac_wipe_secret 1.026m 2.062ms 1 1 100.00
hmac_test_sha256_vectors 3.183m 5.664ms 1 1 100.00
hmac_test_sha384_vectors 6.238m 12.983ms 1 1 100.00
hmac_test_sha512_vectors 19.250s 486.455us 1 1 100.00
hmac_test_hmac256_vectors 9.980s 305.556us 1 1 100.00
hmac_test_hmac384_vectors 7.740s 4.636ms 1 1 100.00
hmac_test_hmac512_vectors 8.680s 875.105us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.760s 487.999us 1 1 100.00
hmac_long_msg 36.380s 11.865ms 1 1 100.00
hmac_back_pressure 27.830s 707.580us 1 1 100.00
hmac_datapath_stress 11.606m 9.735ms 1 1 100.00
hmac_burst_wr 19.120s 500.745us 1 1 100.00
hmac_error 1.007m 1.659ms 1 1 100.00
hmac_wipe_secret 1.026m 2.062ms 1 1 100.00
hmac_test_sha256_vectors 3.183m 5.664ms 1 1 100.00
hmac_test_sha384_vectors 6.238m 12.983ms 1 1 100.00
hmac_test_sha512_vectors 19.250s 486.455us 1 1 100.00
hmac_test_hmac256_vectors 9.980s 305.556us 1 1 100.00
hmac_test_hmac384_vectors 7.740s 4.636ms 1 1 100.00
hmac_test_hmac512_vectors 8.680s 875.105us 1 1 100.00
hmac_stress_all 9.412m 21.324ms 1 1 100.00
V2 stress_all hmac_stress_all 9.412m 21.324ms 1 1 100.00
V2 alert_test hmac_alert_test 1.310s 70.085us 1 1 100.00
V2 intr_test hmac_intr_test 1.570s 44.867us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.370s 133.111us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.370s 133.111us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.540s 16.709us 1 1 100.00
hmac_csr_rw 1.500s 35.578us 1 1 100.00
hmac_csr_aliasing 3.250s 165.713us 1 1 100.00
hmac_same_csr_outstanding 1.890s 48.205us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.540s 16.709us 1 1 100.00
hmac_csr_rw 1.500s 35.578us 1 1 100.00
hmac_csr_aliasing 3.250s 165.713us 1 1 100.00
hmac_same_csr_outstanding 1.890s 48.205us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.650s 147.431us 1 1 100.00
hmac_tl_intg_err 2.340s 95.155us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.340s 95.155us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.760s 487.999us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.090s 195.067us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.616m 13.143ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.770s 9.513us 1 1 100.00
TOTAL 28 28 100.00