I2C Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: `b69339b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	32.310s	4.159ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.790s	2.082ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.490s	91.096us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.640s	15.795us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.900s	113.507us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.570s	272.020us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.650s	32.092us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.640s	15.795us	1	1	100.00
		i2c_csr_aliasing	2.570s	272.020us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.560s	909.844us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	23.980m	20.626ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	40.980s	2.626ms	1	1	100.00
V2	host_override	i2c_host_override	1.660s	28.188us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	59.160s	14.906ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	25.670s	2.741ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.120s	505.948us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.620s	5.979ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.640s	159.439us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	47.780s	2.883ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	14.880s	939.629us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.520s	34.015us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.780s	2.627ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	39.180s	58.128ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.150s	1.050ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	19.240s	632.597us	1	1	100.00
		i2c_target_intr_smoke	5.990s	1.386ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.530s	200.392us	1	1	100.00
		i2c_target_fifo_reset_tx	1.730s	155.898us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	16.630s	11.718ms	1	1	100.00
		i2c_target_stress_rd	19.240s	632.597us	1	1	100.00
		i2c_target_intr_stress_wr	24.780s	17.670ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.520s	5.793ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	35.710s	5.929ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.520s	4.734ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	20.240s	10.004ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.490s	6.531ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.810s	118.809us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	40.980s	2.626ms	1	1	100.00
		i2c_host_perf_precise	15.480s	2.203ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	14.880s	939.629us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.890s	11.740us	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.620s	1.373ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.870s	588.499us	1	1	100.00
		i2c_target_nack_txstretch	1.940s	832.247us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.530s	488.678us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.360s	402.189us	1	1	100.00
V2	alert_test	i2c_alert_test	1.540s	40.554us	1	1	100.00
V2	intr_test	i2c_intr_test	1.440s	28.286us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.080s	217.479us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.080s	217.479us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.490s	91.096us	1	1	100.00
		i2c_csr_rw	1.640s	15.795us	1	1	100.00
		i2c_csr_aliasing	2.570s	272.020us	1	1	100.00
		i2c_same_csr_outstanding	1.900s	328.927us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.490s	91.096us	1	1	100.00
		i2c_csr_rw	1.640s	15.795us	1	1	100.00
		i2c_csr_aliasing	2.570s	272.020us	1	1	100.00
		i2c_same_csr_outstanding	1.900s	328.927us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.080s	313.635us	1	1	100.00
		i2c_sec_cm	1.790s	42.128us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.080s	313.635us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	23.990s	648.378us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.040s	142.863us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.700s	2.523ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.25629207215832306304833546200049182478000811009715766135892647925022100900831
    Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 648378075 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 648378075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.90695417704713610285274872681668974715080071228715285136052991101481868234373
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2523371282 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2523371282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.63620633412151732050666290880184451993826687050673370127332942694544711769559
Line 240, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20626207012 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @24088898

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.11693588652503144130773758072883419839262329691166524546204594279691932493824
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 142863146 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 142863146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.105562079978840332970582130766388453501234686052766550280540745750059766485664
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10004330575 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10004330575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.46185934826840622661177586085983571709585813144180137692158763572988697688076
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  34015001 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xf0dd1a94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  34015001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 0.i2c_target_tx_stretch_ctrl.75579377732214347199341893651562171958315979125168044672568937761594707997392
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```